NCP81174
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13
start up smoothly under an output pre−biased condition
without discharging the output before ramping up.
Before the output soft start begins, an internal switch will
be turned on to discharge the external filter cap C_REFIN
connected to the REFIN pin to reset the DAC setting, the
typical on resistance of the switch is around 6 Ws. After the
discharging, internal switch will be turned off to allow
external C_REFIN cap to recharge. After 100 ms, the output
voltage ramps up with a fixed slew rate of 1.3 mV/mS.
The circuit can be set to start from either all the phases
when the input power rails are all available or from phase 1
when only one input power rail is available by presetting the
power mode from PSI pin (See Power Operation Modes).
5V Shunt Regulator
The NCP81174 has an internal shunt regulator to generate
5 V from the external power supply (e.g. 12 V). It is
recommended to connect three 0603 resistors (450 W each)
in parallel from a 12 V power supply to the VCC pin.
Thermal Compensation Amplifier with VDRP and
VDFB pins
Thermal compensation amplifier is an internal amplifier
in the path of droop current feedback for additional
adjustment of the gain of summing current and temperature
compensation. The way thermal compensation is
implemented separately ensures minimum interference to
the voltage loop compensation network.
PWM Comparators with Hysteresis and 3
rd
state of
PWM Outputs
Four PWM comparators receive an error signal at their
non−inverting input and one of the triangle waves at its
inverting input. The output of each comparator generates the
PWM outputs G1, G2, G3 and G4.
During the steady state operation, the duty cycle will
center on the valley of the triangle waveform, with steady
state duty cycle calculated by Vout/Vin. During a transient
event, both high and low comparator output transitions shift
phase to the points where the error signal intersects the down
and up ramp of the triangle wave.
PWM signals vary between high and low in all phase
operation or forced PWM mode. In power saving mode
(PS2), PWM signals vary between high and mid level to
allow diode emulation.
2/3/4 Phase Operation
Besides 4−phase, the part can be configured to run in 2 or
3−phase mode. In 2−phase mode, phase 1 and 3 should be
used to drive the external gate drivers, gate outputs G2 and
G4 should be grounded. In 3−phase mode, gate output G4
should be grounded. The current sense inputs of the unused
channels should be connected to the Vcore output.
Differential Current Sense Amplifiers and Summing
Amplifier
Four differential amplifiers are provided to sense the
output current of each phase. The inputs of each current
sense amplifier must be connected across the current sensing
element of the phase controlled by the corresponding gate
output (G1, G2, G3, or G4). If a phase is unused, the
differential inputs to that phase’s current sense amplifier
must be shorted together and connected to the output.
A voltage is generated across the current sense element
(such as an inductor or sense resistor) by the current flowing
in that phase. The outputs of four current amplifiers are fed
into a summing amplifier to have a summed−up output
(CSSUM). Signal of CSSUM combines information of total
current of all phases in operation. The gain from the total
sense current input to CSSUM (A
CSSUM) is ~3.93.
The output of the current sense amplifiers are used to
control three functions. First, the output controls the
adaptive voltage positioning, where the output voltage is
actively controlled according to the output current. Second,
the output signal is fed to the current limit circuit. This again
is the summed current of all phases in operation. Finally, the
individual phase current is connected to the PWM
comparator. In this way current balance is accomplished.
Undervoltage Lockout (VCC UVLO) and 12VMON
VCC is constantly monitored for undervoltage lockout
(UVLO). Line input (normally 12V) is monitored for
undervoltage lockout through 12VMON pin by connecting
an appropriate resistor divider from line input to the
12VMON input. The setting of the resistor divider should
make the 12VMON voltage less than 4 V at all time. During
power-up, both VCC and 12VMON will be monitored. Only
after they exceed their individual UVLO thresholds, the full
circuit will be activated and ready for soft start if the enable
pin is also valid. Both UVLO comparators have hysteresis
to avoid chattering. The second function of 12VMON pin is
to provide feed-forward input voltage information in PS2
mode, see Power Operation Mode section.
Over Current Protection and Under Voltage Protection
A programmable overcurrent function is incorporated
within the IC. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin (0~2 V)
sets the maximum output current the converter can produce.
The VREF pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the VREF pin sets the
limit above useful levels − effectively disabling overcurrent
shutdown. The comparator non−inverting input is the
summed current information from the current sense
amplifier. The overcurrent event will set PWM low for the
rest of the cycle when the current information exceeds the
voltage at the ILIM pin. If the overcurrent continuously
happens and the output will eventually hit the Under Voltage
Protection (UVP) limit and it will be a latched event. The
UVP limit is set to 50% below the REFIN voltage. The
PWM outputs will stay at mid state until the V
CC
voltage is
removed and re−applied, or the ENABLE input is brought
low and then high.
