ISL6141CBZA-T Datasheet ISL6141IBZA, ISL6141CBZA-T, ISL6141CBZA | P13-P15

Inrush Current Control

The primary function of the ISL6141 hot plug controller is to

control the inrush current. When a board is plugged into a

live backplane, the input capacitors of the board’s power

supply circuit can produce large current transients as they

charge up. This can cause glitches on the system power

supply (which can affect other boards!), as well as possibly

cause some permanent damage to the power supply.

The key to allowing boards to be inserted into a live

backplane is to turn on the power to the board in a controlled

manner, usually by limiting the current allowed to flow

through a FET switch, until the input capacitors are fully

charged. At that point, the FET is fully on, for the smallest

voltage drop across it. Figure 25 below illustrates the typical

inrush current response resulting from a hot insertion for the

following conditions:

•V

= -48V, Rsense = 0.02 (2.5A current limit)

• C1 = 150nF, C2 = 3.3nF, R3 = 18k

•I

Inrush

= 50A (100F/3.3nF) = 1.5A

•C

= 100uF, R

= 150 (48V/150 = 320mA)

After the contact bounce subsides the UVLO and UV criteria

are quickly met and the GATE begins to ramp up. As the

GATE reaches approximately 4V with respect to the source,

the FET begins to turn on allowing current to charge the load

capacitor. As the drain to source voltage begins to drop, the

feedback network of C2 and R3 hold the GATE constant, in

this case limiting the current to approximately 1.3A. When

the DRAIN voltage completes its ramp down the load current

remains constant at 320mA as the GATE voltage increases

to its final value.

Electronic Circuit Breaker/Current Limit

The ISL6141/51 features programmable current limiting with a

fixed 600s time-out period to protect against excessive

supply or fault currents. The IntelliTrip

electronic circuit

breaker is capable of detecting both hard faults, and less

severe Over-Current conditions.

The Over-Current trip point is determined by R1 (Eq. #3) also

referred to as Rsense. When the voltage across this resistor

exceeds 50mV, the current limit regulator will turn on, and the

GATE will be pulled lower (to ~4V) to regulate current through

the FET at 50mV/Rsense. If the fault persists and current

limiting exceeds the 600s time-out period, the FET will be

turned off by discharging the GATE pin to V

. This will

enable the Over-Current latch and the PWRGD

/PWRGD

output will transition to the inactive state to indicate power is

no longer good. To clear the latch and initiate a normal power-

up sequence, the user must either power down the system

(below the UVLO voltage), or toggle the UV pin below and

above its threshold (usually with an external transistor). Figure

26 below shows the Over-Current shut down and current

limiting response for a 10 short to ground on the output. With

a 10 short and a -48V supply, the initial fault current is

approximately 4.8A, producing a voltage drop across the

0.02 sense resistor of 95mV, roughly two times the Over-

Current threshold of 50mV. This enables the 600s timer and

the GATE is quickly pulled low to limit the current to 2.5A

(50mV/Rsense). The fault condition persists for the duration of

the time-out period and the GATE is latched off in about

670s. There is a short filter (3s nominal) on the comparator,

so current transients shorter than this will be ignored. Longer

transients will initiate the GATE pull down, current limiting, and

the timer. If the fault current goes away before the time-out

period expires the device will exit the current limiting mode

and resume normal operation.

FIGURE 25. INRUSH CURRENT LIMITING FOR A HOT

INSERTION

FIGURE 26. CURRENT LIMITING AND TIMEOUT

ISL6141, ISL6151

In addition to the above current limit and 600s time-out,

there is a Hard Fault comparator to respond to short circuits

with an immediate GATE shutdown (typically 10s) and a

single retry. The trip point of this comparator is set ~4 times

(210mV) higher than the Over-Current threshold of 50mV. If

the Hard Fault comparator trip point is exceeded, a hard pull

down current (350mA) is enabled to quickly pull down the

GATE and momentarily turn off the FET. The fast shutdown

resets the 600s timer and is followed by a soft start, single

retry event. If the fault is still present after the GATE is slowly

turned on, the current-limit regulator will trip (sense pin

voltage > 50mV), turn on the timer, and limit the current to

50mV/Rsense for 600s before latching the GATE pin low.

Note: Since the 600s timer starts when the SENSE pin

exceeds the 50mV threshold, then depending on the speed of

the current transient exceeding 200mV, it’s possible that the

current limit time-out and shutdown can occur before the Hard

Fault comparator trips (and thus no retry). Figure 27 illustrates

the Hard Fault response with a zero ohm short circuit at the

output.

As in the Over-Current response discussed previously the

supply is set at -48V and the current limit is set at 2.5A. After

the initial gate shutdown (10s) a soft start is initiated with

the short circuit still present. As the GATE slowly turns on the

current ramps up and exceeds the Over-Current threshold

(50mV) enabling the timer and current limiting. The fault

remains for the duration of the time-out period and the GATE

pin is quickly pulled low and latched off requiring a UVLO or

UV reset to resume normal operation (assuming the fault

has gone away).

Applications: OV and UV

The UV and OV pins can be used to detect Over-Voltage

and Under-Voltage conditions on the input supply and

quickly shut down the external FET. Each pin is tied to an

internal comparator with a nominal reference of 1.255V. A

resistor divider between the V

(gnd) and V

is typically

used to set the trip points on the UV and OV pins. If the

voltage on the UV pin is above its threshold and the voltage

on the OV pin is below its threshold, the supply is within its

operating range and the GATE will be allowed to turn on, or

remain on. If the UV pin voltage drops below its high to low

threshold, or the OV pin voltage increases above its low to

high threshold, the GATE pin will be pulled low, turning off

the FET until the supply is back within tolerance.

The OV and UV inputs are high impedance, so the value of

the external resistor divider is not critical with respect to input

current. Therefore, the next consideration is total current; the

resistors will always draw current, equal to the supply

voltage divided by the total resistance of the divider

(R4+R5+R6) so the values should be chosen high enough to

get an acceptable current. However, to the extent that the

noise on the power supply can be transmitted to the pins, the

resistor values might be chosen to be lower. A filter capacitor

from UV to V

or OV to V

is a possibility, if certain

transients need to be filtered. (Note that even some

transients which will momentarily shut off the GATE might

recover fast enough such that the GATE or the output

current does not even see the interruption).

Finally, take into account whether the resistor values are

readily available, or need to be custom ordered. Tolerances

of 1% are recommended for accuracy. Note that for a typical

48V system (with a 43V to 72V range), the 43V or 72V is

being divided down to 1.255V, a significant scaling factor.

For UV, the ratio is roughly 35 times; every 3mV change on

the UV pin represents roughly 0.1V change of power supply

voltage. Conversely, an error of 3mV (due to the resistors,

for example) results in an error of 0.1V for the supply trip

point. The OV ratio is around 60. So the accuracy of the

resistors comes into play.

The hysteresis of the comparators is also multiplied by the

scale factor of 35 for the UV pin (35 * 135mV = 4.7V of

hysteresis at the power supply) and 60 for the OV pin (60 *

25mV = 1.5V of hysteresis at the power supply).

With the three resistors, the UV equation is based on the

simple resistor divider:

1.255 = V

* (R5 + R6)/(R4 + R5 + R6) or

= 1.255 (R4 + R5 + R6)/(R5 + R6)

Similarly, for OV:

1.255 = V

* (R6)/(R4 + R5 + R6) or

= 1.255 (R4 + R5 + R6)/(R6)

Note that there are two equations, but 3 unknowns. Because

of the scale factor, R4 has to be much bigger than the other

two; chose its value first, to set the current (for example, 50V /

500k draws 100A), and then the other two will be in the

10k range. Solve the two equations for two unknowns. Note

that some iteration may be necessary to select values that

FIGURE 27. HARD FAULT SHUTDOWN AND RETRY

ISL6141, ISL6151

meet the requirement, and are also readily available standard

values.

The three resistor divider (R4, R5, R6) is the recommended

approach for most cases. But if acceptable values can’t be

found, then consider 2 separate resistor dividers (one for

each pin, both from V

to V

). This also allows the user to

adjust or trim either trip point independently. Some

applications employ a short pin ground on the connector tied

to R4 to ensure the hot plug device is fully powered up

before the UV and OV pins (tied to the short pin ground) are

biased. This ensures proper control of the GATE is

maintained during power up. This is not a requirement for

the ISL6141/51 however the circuit will perform properly if a

short pin scheme is implemented (reference Figure 34).

Supply ramping

As previously mentioned the UV and OV pins can be used to

detect under and Over-Voltage conditions on the input

supply. Figures 28 and 29 illustrate the GATE shutdown

response and the UV/OV hysteresis as a typical power

supply is ramped from 0 to 80V, and then from 80V to 0V.

As the supply ramps up, the UV threshold is reached at

43.6V and the FET begins to turn on. Within 40ms the GATE

is fully on and the device is operating normally. As the supply

continues to ramp up the Over-Voltage threshold is

exceeded at approximately 70.5V and the GATE is quickly

shut down as expected. In figure 29 the GATE voltage

begins in the off state as the supply voltage is above the OV

set point. As the supply voltage decreases the GATE turns

on at about 69V (roughly a 1.5 volt hysteresis). Some 800ms

later (a characteristic of the supply used) the UV high to low

threshold is met at approximately 38.5 volts (about 5.0V of

hysteresis) and the GATE is shut off.

Applications: PWRGD/PWRGD

The PWRGD/PWRGD outputs are typically used to directly

enable a power module, such as a DC/DC converter. The

PWRGD

(ISL6141) is used for modules with active low

enable (L version), and PWRGD (ISL6151) for those with

active high enable (H version). The modules usually have a

pull-up device built-in, as well as an internal clamp. If not, an

external pull-up resistor may be needed. If the pin is not

used, it can be left open.

For both versions at initial start-up, when the DRAIN to V

voltage differential is less than 1.3V and the GATE voltage is

within 2.5V (V

) of its normal operating voltage (13.6V),

power is considered good and the PWRGD

/PWRGD pins

will go active. At this point the output is latched and the

DRAIN is no longer criticized. The latch is reset by any of the

signals that shut off the GATE (Over-Voltage, Under-Voltage;

Under-Voltage-Lock-Out; Over-Current Time-Out or

powering down). In this case the PWRGD

/PWRGD output

will go inactive, indicating power is no longer good.

ISL6141 (L version; Figure 30): Under normal conditions

(DRAIN voltage - V

< V

, and V

GATE

- V

GATE

< V

)

the Q2 DMOS will turn on, pulling PWRGD

low, enabling the

module.

FIGURE 28. SUPPLY RAMP-UP

FIGURE 29. SUPPLY RAMP-DOWN

PWRGD

DRAIN

VDD

VIN+

VIN-

/OFF

VOUT+

VOUT-

ACTIVE LOW

ENABLE

MODULE

(SECTION OF) ISL6141

(L VERSION)

FIGURE 30. ACTIVE LOW ENABLE MODULE

GATE



GATE

LOGIC

LATCH

ISL6141, ISL6151

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

ISL6141CBZA-T

Mfr. #:

Buy ISL6141CBZA-T

Manufacturer:

Renesas / Intersil

Description:

Hot Swap Voltage Controllers W/ANNEAL 8LD 0+70 LWSIDE HOTPLUGCNTRLR

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ISL6141CBZA-T

ISL6141CBZA-T

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