N01S830HA, N01S830BA
www.onsemi.com
3
Table 3. CONTROL SIGNAL DESCRIPTIONS
Signal DescriptionName
Mode
Used
HOLD SPI and
DUAL
Hold A high level is required for normal operation. Once the device is selected and a serial sequence
is started, this input may be taken low to pause serial communication without resetting the serial
sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low,
the HOLD function will not be invoked until the next SCK high to low transition. The device must
remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are
inputs are ignored. To resume operations, HOLD
must be pulled high while the SCK pin is low.
Lowering the HOLD
input at any time will take to SO output to High-Z.
VBAT SPI and
DUAL
Battery Voltage Provides the battery power connection to retain data in battery backed mode.
SIO0 - 1 DUAL Serial Data
Input / Output
Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out
after the falling edge of SCK. The instruction must be set after power-up to enable the DUAL
access mode.
SIO0 - 3 QUAD Serial Data
Input / Output
Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out
after the falling edge of SCK. The instruction must be set after power-up to enable the QUAD
access mode.
Basic Operation
The 1 Mb serial SRAM is designed to interface directly
with a standard Serial Peripheral Interface (SPI) common on
many standard micro-controllers in the default state. It may
also interface with other non-SPI ports by programming
discrete I/O lines to operate the device.
The serial SRAM contains an 8-bit instruction register and
is accessed via the SI pin. The CS
pin must be low and the
HOLD
pin must be high for the entire operation. Data is
sampled on the first rising edge of SCK after CS
goes low.
If the clock line is shared, the user can assert the HOLD
input
and place the device into a Hold mode. After releasing the
HOLD
pin, the operation will resume from the point where
it was held. The Hold operation is only supported in SPI and
DUAL modes.
By programming the device through a command
instruction, the dual and quad access modes may be initiated.
In these modes, multiplexed I/O lines take the place of the
SPI SI and SO pins and along with the CS and SCK control
the device in a SPI-like, two bit (DUAL) and four bit
(QUAD) wide serial manner. Once the device is put into
either the DUAL or QUAD mode, the device will remain
operating in that mode until powered down or the Reset
Mode operation is programmed.
The following table contains the possible instructions and
formats. All instructions, addresses and data are transferred
MSB first and LSB last.
Table 4. INSTRUCTION SET
Instruction Command Description
READ 03h Read data from memory starting at selected address
WRITE 02h Write (program) data to memory starting at selected address
EQIO 38h Enable QUAD I/O access
EDIO 3Bh Enable DUAL I/O access
RSTQIO FFh Reset from QUAD and DUAL to SPI I/O access
RDMR 05h Read mode register
WRMR 01h Write mode register
