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7
Figure 8. QUAD Write Sequence
CS
043251698107
11
SCK
12 13
Instruction
SIO[3:0] A5 A0
24−bit address
C1 C0 A4 A3 A2 A1 H0 L0 H1 L1 H2 L2 Hn Ln
Data in
MSB MSB
Notes:
C[1:0] = 02h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
READ Mode Register (RDMR)
This instruction provides the ability to read the mode
register. The register may be read at any time including
during a Write operation. The Read Mode Register
operation is executed by driving CS low, then sending the
RDMR instruction to the device. Immediately after the
instruction, the device outputs data on the SO (SIO0-3)
pin(s). To complete the operation, drive CS
high to terminate
the register read.
Figure 9. SPI Read Mode Register Sequence (RDMR)
CS
Instruction
SI
04325169810711
SCK
7 6543210High−Z
Mode Register Data Out
SO
00 000 10
12 13 14 15
1
Figure 10. DUAL Read Mode Register Sequence (RDMR)
C[3:0] = 05hNotes:
CS
Instruction
0321
SCK
C3 C2 H L
MSB
Mode Bits
SIO[1:0]
45
LHC1 C0
67
N01S830HA, N01S830BA
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8
Figure 11. QUAD Read Mode Register Sequence (RDMR)
C[1:0] = 05hNotes:
CS
Instruction
0321
SCK
C1 C0 H L
MSB
Mode Bits
SIO[3:0]
Write Mode Register (WRMR)
This instruction provides the ability to write the mode
register. The Write Mode Register operation is executed by
driving CS
low, then sending the WRMR instruction to the
device. Immediately after the instruction, the data is driven
to the device on the SO (SIO0-3) pin(s). To complete the
operation, drive CS high to terminate the register write.
Figure 12. SPI Write Mode Register Sequence
CS
Instruction
SI
04325169810711
SCK
7 6543210
High−Z
Mode Register Data In
SO
00 000 10
12 13 14 15
0
Figure 13. DUAL Write Mode Register Sequence
C[3:0] = 01hNotes:
CS
Instruction
0321
SCK
C3 C2 H L
MSB
Mode Bits
SIO[1:0]
45
LHC1 C0
67
Figure 14. QUAD Write Mode Register Sequence
CS
Instruction
0321
SCK
C1 C0 H L
C[1:0] = 01hNotes:
MSB
Mode Bits
SIO[3:0]
N01S830HA, N01S830BA
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9
Table 5. MODE REGISTER
Bit Function
0 Hold Function
1 = Hold function disabled
0 = Hold function enabled (Default)
1 Reserved
2 Reserved
3 Reserved
4 Reserved
5 Reserved
6
Operating Mode
Bit 7 Bit 6
0 0 = Word Mode
1 0 = Page Mode
0 1 = Burst Mode (Default)
1 1 = Reserved
7
Power-Up State
The serial SRAM enters a know state at power-up time.
The device is in low-power standby state with CS
= 1. A low
level on CS
is required to enter a active state.
Battery Back-Up Operation
The Battery Back-Up function is available on the BBU
version of the serial SRAM. This version of the SRAM
cannot operate in the QUAD mode since the SIO3 input is
used for the VBAT connection. A standard coin cell battery
should be connected to the VBAT pin. On chip circuitry
monitors the V
CC
pin and when it is determined that the main
V
CC
power supply is turning off, the device automatically
switches the memory array to VBAT power input. When in
battery back-up mode and 3.0 to 3.4 V power supplied to the
VBAT input, memory data is retained in the SRAM array
and all existing interface and operating mode information is
retained.
Figure 15. Battery Back-Up Version Schematics
SO
NC
VSS
VCC
SCK
SI
Coin Cell Battery
3.0 to 3.4 V
VBAT
Serial
SRAM
CS
Table 6. ABSOLUTE MAXIMUM RATINGS
Item Symbol Rating Units
Voltage on any pin relative to V
SS
V
IN,OUT
–0.3 to V
CC
+ 0.3 V
Voltage on V
CC
Supply Relative to V
SS
V
CC
–0.3 to 5.5 V
Power Dissipation P
D
500 mW
Storage Temperature T
STG
−40°C to 125°C °C
Ambient Temperature Under Bias T
A
−40°C to +125°C °C
Soldering Temperature and Time T
SOLDER
260°C, 10 sec °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 7. OPERATING CHARACTERISTICS (Industrial (I): T
A
= −40°C to +85°C, Automotive (E): T
A
= −40°C to +125°C)
Item Symbol Test Conditions Min Typ (Note 1) Max Units
Supply Voltage V
CC
2.5 5.5 V
Data Retention Voltage V
DR
1.0 V
Input High Voltage V
IH
0.7 V
CC
V
CC
+ 0.3 V
Input Low Voltage V
IL
−0.3 0.1 V
CC
V
Output High Voltage V
OH
I
OH
= −0.4 mA V
CC
− 0.2 V
Output Low Voltage V
OL
I
OL
= 1 mA 0.2 V
Input Leakage Current I
LI
CS = V
CC
, V
IN
= 0 to V
CC
1.0
mA
Output Leakage Current I
LO
CS = V
CC
, V
OUT
= 0 to V
CC
1.0
mA
Operating Current I
CC
f = 20 MHz, I
OUT
= 0, SPI / DUAL 10
mA
f = 20 MHz, I
OUT
= 0, QUAD 20
Standby Current I
SB
CS = V
CC
, V
IN
= V
SS
or V
CC
, I−Temp 4 10 mA
CS = V
CC
, V
IN
= V
SS
or V
CC
, E−Temp 20
1. Typical values are measured at V
CC
= V
CC
Typ., T
A
= 25°C and are not 100% tested.

N01S830HAT22I

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
SRAM 1MB UltraLow Pwr Serial SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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