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CYRF89435-68LTXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
CYRF89435
Document Number: 001-76581 Rev. *G Page 10 of 39
Pin Definitions
Pin No Pin name Pin Description
1 P1[3]/SCLK
[2]
Digital I/O, Analog I/O, SPI CLK
2 P1[1]/MOSI
[1]
Digital I/O, Analog I/O, TC CLK, I2C SCL, SPI MOSI
3 GND Ground connection
4, 20, 25, 33,
34, 37, 40
VDD Core power supply voltage. Connect all VDD pins to VOUT pin.
5 DNU Do not use
6 DNU Do not use
7 FIFO FIFO status indicator bit
8 DNU Do not use
9P1[0]
[1]
Analog I/O, Digital I/O, TC DATA, I2C SDA
10, 21, 24 VIN Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator
11 P1[2] Analog I/O, Digital I/O
12 P1[4] Analog I/O, Digital I/O, EXT CLK
13 XRES Active high external reset with internal pull-down
14 SPI_SS Enable input for SPI, active low. Also used to bring device out of sleep state.
15 PKT Transmit/receive packet status indicator bit
16 SPI_CLK Clock input for SPI interface
17 SPI_MOSI Data input for the SPI bus
18 SPI_MISO Data output (tristate when not active)
19 RST_n RST_n Low: Chip shutdown to conserve power. Register values lost
RST_n High: Turn on chip, registers restored to default value
22 VOUT 1.8 V output from on-chip LDO. Connect to all VDD pins, do not connect to external loads.
23 P0[4] Analog I/O, Digital I/O, VREF
26 XTALO Output of the crystal oscillator gain block
27 XTALI Input to the crystal oscillator gain block
28 P0[7] Analog I/O, Digital I/O,SPI CLK
29 P0[3] Analog I/O, Digital I/O, Integrating input
30 P0[1] Analog I/O, Digital I/O, Integrating input
31 P2[5] Analog I/O, Digital I/O, XTAL Out
32 P2[3] Analog I/O, Digital I/O, XTAL In
35 ANTb Differential RF input/output. Each of these pins must be DC grounded, 20 kȍ or less
36 ANT Differential RF input/output. Each of these pins must be DC grounded, 20 kȍ or less
38 P1[7]/SS_N Digital I/O, Analog I/O, I2C SCL, SPI SS
39 P1[5]/MISO Digital I/O, Analog I/O, I2C SDA, SPI MISO
Notes
1. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
2. Alternate SPI clock.
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CYRF89435
Document Number: 001-76581 Rev. *G Page 11 of 39
Electrical Specifications – PSoC Core
This section presents the DC and AC electrical specifications of the CYRF89435 PSoC devices. For the latest electrical specifications,
confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 4. Voltage versus CPU Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Operating Temperature
3.6 V
750 kHz
24 MHz
CPU Frequency
VIN Voltage
1.9 V
3 MHz
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Table 2. Absolute Maximum Ratings
Symbol Description Conditions Min Typ Max Units
T
STG
Storage temperature Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55 25 125 °C
V
IN
[3]
– 1.9 – 3.63 V
V
IO
DC input voltage – –0.5 – V
IN
+ 0.5 V
V
IOZ
[4]
DC voltage applied to tristate – –0.5 – V
IN
+ 0.5 V
I
MIO
Maximum current into any port pin – –25 – +50 mA
ESD Electrostatic discharge voltage Human body model ESD
i) RF pins (ANT, ANTb)
ii) Analog pins (XTALi, XTALo)
iii) Remaining pins
500
500
2000
– – V
LU Latch-up current In accordance with JESD78 standard – – 140 mA
Table 3. Operating Temperature
Symbol Description Conditions Min Typ Max Units
T
A
Ambient temperature – 0 – 70 °C
Notes
3. Program the device at 3.3 V only. Hence use MiniProg3 only as MiniProg1 does not support programming at 3.3 V.
4. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above V
IN
.
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CYRF89435
Document Number: 001-76581 Rev. *G Page 12 of 39
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 4. DC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
V
IN
[5, 6, 7, 8]
Supply voltage Refer the table DC POR and LVD
Specifications on page 17
1.9 – 3.6 V
I
DD24
Supply current, IMO = 24 MHz Conditions are V
IN
d 3.0 V,
T
A
= 25 °C, CPU = 24 MHz.
CapSense running at 12 MHz,
no I/O sourcing current
– 2.88 4.00 mA
I
DD12
Supply current, IMO = 12 MHz Conditions are V
IN
d 3.0 V,
T
A
= 25 °C, CPU = 12 MHz.
CapSense running at 12 MHz,
no I/O sourcing current
– 1.71 2.60 mA
I
DD6
Supply current, IMO = 6 MHz Conditions are V
IN
d 3.0 V,
T
A
= 25 °C, CPU = 6 MHz.
CapSense running at 6 MHz,
no I/O sourcing current
– 1.16 1.80 mA
I
DDAVG10
Average supply current per
sensor
One sensor scanned at 10 ms rate – 250 – PA
I
DDAVG100
Average supply current per
sensor
One sensor scanned
at 100 ms rate
– 25 – PA
I
DDAVG500
Average supply current per
sensor
One sensor scanned
at 500 ms rate
– 7 – PA
I
SB0
Deep sleep current V
IN
d 3.0 V, T
A
= 25 °C,
I/O regulator turned off
– 0.10 1.05 PA
I
SB1
Standby current with POR, LVD
and sleep timer
V
IN
d 3.0 V, T
A
= 25 °C,
I/O regulator turned off
– 1.07 1.50 PA
I
SBI2C
Standby current with I
2
C enabled Conditions are V
IN
= 3.3 V,
T
A
= 25 °C and CPU = 24 MHz
– 1.64 – PA
Notes
5. If powering down in standby sleep mode, to properly detect and recover from a V
IN
brown out condition any of the following actions must be taken:
Bring the device out of sleep before powering down.
Assure that V
IN
falls below 100 mV before powering back up.
Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
Increase the buzz rate to assure that the falling edge of V
IN
is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers, refer to the CY8C20X36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows V
IN
brown out conditions to be detected for edge rates slower than 1V/ms.
6. Always greater than 50 mV above V
PPOR1
voltage for falling supply.
7. Always greater than 50 mV above V
PPOR2
voltage for falling supply.
8. Always greater than 50 mV above V
PPOR3
voltage for falling supply.
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

CYRF89435-68LTXC

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Manufacturer:
Cypress Semiconductor
Description:
RF Transceiver Wireless Capacitive Touch
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