CYRF89435-68LTXC Datasheet CYRF89435-68LTXC | P7-P9

CYRF89435

Document Number: 001-76581 Rev. *G Page 7 of 39

Development Tools

PSoC Designer™ is the revolutionary integrated design

environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

■ In-circuit emulation

■ Built-in support for communication interfaces:

❐ Hardware and software I

C slaves and masters

❐ SPI master and slave, and wireless

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

PSoC Designer Software Subsystems

Design Entry

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are analog-to-digital converters (ADCs),

digital-to-analog converters (DACs), amplifiers, and filters.

Configure the user modules for your chosen application and

connect them to each other and to the proper pins. Then

generate your project. This prepopulates your project with APIs

and libraries that you can use to program your application.

The tool also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

reconfiguration makes it possible to change configurations at run

time. In essence, this lets you to use more than 100 percent of

PSoC’s resources for an application.

Code Generation Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and linked

with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also lets you to create a trace buffer of registers and memory

locations of interest.

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an Online Support

Forum to aid the designer.

In-Circuit Emulator

A low-cost, high-functionality in-circuit emulator (ICE) is

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24 MHz) operation.

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Document Number: 001-76581 Rev. *G Page 8 of 39

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed-function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and lowering inventory costs. These

configurable resources, called PSoC blocks, have the ability to

implement a wide variety of user-selectable functions. The PSoC

development process is:

1. Select user modules.

2. Configure user modules.

3. Organize and connect.

4. Generate, verify, and debug.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware

peripheral components called “user modules”. User modules

make selecting and implementing peripheral devices, both

analog and digital, simple.

Configure User Modules

Each user module that you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a PWM

User Module configures one or more digital PSoC blocks, one

for each eight bits of resolution. Using these parameters, you can

establish the pulse width and duty cycle. Configure the

parameters and properties to correspond to your chosen

application. Enter values directly or by selecting values from

drop-down menus. All of the user modules are documented in

datasheets that may be viewed directly in PSoC Designer or on

the Cypress website. These user module datasheets explain the

internal operation of the user module and provide performance

specifications. Each datasheet describes the use of each user

module parameter, and other information that you may need to

successfully implement your design.

Organize and Connect

Build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. Perform the selection,

configuration, and routing so that you have complete control over

all on-chip resources.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move

on to developing code for the project, perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides APIs with high-level functions to control

and respond to hardware events at run time, and interrupt

service routines that you can adapt as needed.

A complete code development environment lets you to develop

and customize your applications in C, assembly language, or

both.

The last step in the development process takes place inside

PSoC Designer’s Debugger (accessed by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full-speed. PSoC Designer debugging

capabilities rival those of systems costing many times more. In

addition to traditional single-step, run-to-breakpoint, and

watch-variable features, the debug interface provides a large

trace buffer. The interface lets you to define complex breakpoint

events that include monitoring address and data bus values,

memory locations, and external signals.

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CYRF89435

Document Number: 001-76581 Rev. *G Page 9 of 39

Pinouts

The CYRF89435 PRoC-CS device is available in a 40-pin QFN package, which is illustrated in the following table. Every port pin

(labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, V

, and XRES are not capable of

Digital I/O.

Figure 3. 40-pin QFN pinout

40 39 38 37 36 35 34 33 32 31

11 12 13 14 15 16 17 18 19 20

QFN

(Top View)

MISO

RST_n

P0[7]

DNU

FIFO

DNU

P1[0]

VIN

XRES

P1[4]

P1[2]

SPI_SS

VDD

P1[7]

XTALi

ANT

VDD

P1[1]

GND

P1[3]

PKT

MOSI

CLK

ANTb

P2[3]

VDD

P2[5]

XTALo

VDD

VOUT

VIN

P0[4]

VDD

VIN

P0[3]

VDD

P1[5]

P0[1]

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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

CYRF89435-68LTXC

Mfr. #:

Buy CYRF89435-68LTXC

Manufacturer:

Cypress Semiconductor

Description:

RF Transceiver Wireless Capacitive Touch

Lifecycle:

New from this manufacturer.

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