HSP43216VC-52Z Datasheet HSP43216JC-52Z, HSP43216VC-52Z | P7-P9

FN3365.10

October 6, 2008

/4 Quadrature Up Convert Processor

The f

/4 Quadrature Up Convert Processor provides the

/4 spectral shift used to construct a real signal from a

complex sample stream. The operation performed is

equivalent to multiplying a quadrature data stream,

i(n)+jq(n), by samples of a complex exponential, e

-j(/2)n

and outputting the real part of that mathematical operation

as given below:

Real { (i (n) + jq(n) ) e

j (n/2)

}

= Real {[i (n) cos (n/2) - q(n) sin (n/2)]

+ j [i (n) sin (n/2) + q(n) cos (n/2)]}

= i (n) cos (n/2) - q(n) sin (n/2)

= i (n) cos (n/2) + q(n) sin (n/2)

(EQ. 3)

In the above operation, a positive f

/4 spectral shift is

imparted on the quadrature input which causes the upper

sideband of the resulting real output to be defined by the

spectral content of the input signal as shown in Figure 3. For

added flexibility, the Up Convert processor may be

configured to impart a negative f

/4 shift on the quadrature

input which generates a real output whose lower sideband is

defined the spectrum of the quadrature input as shown in

Figure 4. The state of the USB/LSB

control input determines

the direction of the spectral shift. If this input is set “High”, a

positive f

/4 shift is introduced by the Up Convert Processor.

If USB/LSB

is asserted “Low”, a negative f

/4 spectral shift

is introduced.

The Up Convert Processor implements the up convert

operation by multiplying the in-phase and quadrature

samples on the upper and lower processing legs by the

nonzero sine and cosine terms in the above expression. The

resulting data is then multiplexed together in the Output Flow

Controller to yield the real output sample stream. The SYNC

control input may be used to align the zero degree phase of

the Up Convert LO with a particular input sample as

described in the Operational Modes Section.

The Up Convert Processor also scales the data streams

output from the Filter Processor as required by the

operational mode. In the modes which employ interpolation,

the Up Convert Processor scales the Filter Processor’s

output by two to compensate for the attenuation of one half

caused by the interpolation process. In down convert and

decimate mode, the filter processor output is also scaled by

two to compensate for the attenuation introduced by the

down covert process. The scaling operations performed are

summarized in Table 4.

Output Data Flow Controller

The Output Flow Controller routes data to the AOUT0-15

and BOUT0-15 output depending on mode of operation. In

decimate by two mode (MODE1-0 = 00), output from the

filter processor’s polyphase branches are summed and

output through AOUT0-15. In Down Convert and Decimate

mode (MODE1-0 = 10), real and imaginary data streams

produced by the down convert process pass are output

directly to AOUT0-15 and BOUT0-15 respectively. In the two

modes using interpolation, MODE1-0 = 01 or 11, with

internal multiplexing enabled, INT/EXT

set high, data sam

ples output from the polyphase branches are internally

multiplexed into a single stream and output via AOUT0-15. If

a mode using interpolation is specified together with external

multiplexing, INT/EXT

set low, the data stream multiplexing

is performed off chip and the data on the upper and lower

processing legs is output through AOUT0-15 and BOUT0-15.

The Output Data Flow Controller also sets the binary format

and precision of the two 16-bit outputs. The data format is

specified as either two’s complement (FMT input low) or

offset binary (FMT input high). The precision of the output

data is set from 8-bits to 16-bits via the round control inputs,

RND2-0. The RND2-0 inputs round the output data to a

precision ranging from 8-bits to 16-bits as specified in Table

5. Saturation logic is incorporated in the output flow

controller to insure that numerical growth associated with a

worst case signal input or rounding condition saturates to a

16-bit value.

FIGURE 3. f

/4 POSITIVE SHIFT: UP CONVERSION

FIGURE 4. f

/4 NEGATIVE SHIFT: DOWN CONVERSION

/4-f

/2 f

/4-f

/2 f

/4-f

/2 f

/4-f

/2 f

TABLE 4. SCALE FACTORS APPLIED BY UP CONVERT

PROCESSOR vs MODE

MODE SCALE FACTOR

Decimate by Two (MODE1-0 = 00) 1.0

Interpolate by Two (MODE1-0 = 01) 2.0

Down Convert and Decimate (MODE1-0 = 10) 2.0

Quadrature to Real (MODE1-0 = 11) 2.0

HSP43216

FN3365.10

October 6, 2008

Operational Modes

Decimate By 2 Filter Mode (Mode1-0 = 00)

The concept of operation for Decimate by Two Filter mode is

most easily understood by comparing the 7 tap transversal

filter implementation to the equivalent polyphase

implementation. The transversal implementation is shown in

Figure 5.

By inspecting the sum-of-products for the decimated output

in Figure 5, it is seen that even indexed input samples are

always multiplied by the even filter coefficients and the odd

samples are always multiplied by the odd coefficients. This

computational partitioning is realized in the polyphase

implementation shown in Figure 6.

In the polyphase implementation, the input data is broken into

even and odd sample streams which are processed by a set

of polyphase filters running at one half of the input data rate.

These filters are designated as even or odd tap filters

depending upon whether the coefficients were derived from

the even or odd indexed coefficients of the original transversal

filter. This architecture only produces the outputs which are

not discarded by the decimation process. NOTE: Since the

only non-zero tap for a halfband filter is the center tap,

the Odd Tap Filter reduces to a delay and multiply

operation.

The operation of the HSP43216 in Decimate by Two mode is

analogous to the polyphase implementation in Figure 6. In

this mode, the internal data paths are routed as shown in

Figure 7A and Figure 7B. The different data flows depend on

whether internal or external multiplexing has been selected

using the INT/EXT

control input. In either case, an input data

stream is decomposed into even and odd sample streams

which are then routed to the even and odd tap polyphase

filters. The output of each polyphase filter is summed and

output via AOUT0-15.

TABLE 5. OUTPUT ROUNDING CONTROL

RND

2-0 ROUND FUNCTION

000 Round output to 8-bits, AOUT15-8 and BOUT15-8, zero

lower bits.

001 Round output to 9-bits, AOUT15-7 and BOUT15-7, zero

lower bits.

010 Round output to 10-bits, AOUT15-6 and BOUT15-6,

zero lower bits.

011 Round output to 11-bits, AOUT15-5 and BOUT15-5,

zero lower bits.

100 Round output to 12-bits, AOUT15-4 and BOUT15-4,

zero lower bits.

101 Round output to 14-bits, AOUT15-2 and BOUT15-2,

zero lower bits.

110 Round output to 16-bits, AOUT15-0 and BOUT15-0.

111 Zero all outputs.

C0 C1 C2 C3 C4 C5 C6

X3,X2,X1,X0

Y(0) = X0(C0)+X1(C1)+X2(C2)+X3(C3)+X4(C4)+X5(C5)+X6(C6)

Y(1) = X1(C0)+X2(C1)+X3(C2)+X4(C3)+X5(C4)+X6(C5)+X7(C6)

Y(2) = X2(C0)+X3(C1)+X4(C2)+X5(C3)+X6(C4)+X7(C5)+X8(C6)

Y(3) = X3(C0)+X4(C1)+X5(C2)+X6(C3)+X7(C4)+X8(C5)+X9(C6)

...,Y1,Y0

..,Y4,Y2,Y0

† Indicates samples discarded by decimation process

†

FIGURE 5. TRANSVERSAL IMPLEMENTATION OF

DECIMATE BY 2 HALFBAND FILTER

C0 C2 C4 C6

...,X4,X2,X0

Y(0) = X0(C0)+X1(C1)+X2(C2)+X3(C3)+X4(C4)+X5(C5)+X6(C6)

Y(1) = X2(C0)+X3(C1)+X4(C2)+X5(C3)+X6(C4)+X7(C5)+X8(C6)

..,Y2,Y1,Y0

C1 C3 C5

ODD TAP FILTER

EVEN TAP FILTER

...,X5,X3,X1

FIGURE 6. POLYPHASE IMPLEMENTATION OF DECIMATE

BY 2 HALFBAND FILTER

HSP43216

FN3365.10

October 6, 2008

If internal multiplexing is selected (INT/EXT = 1), the input data

stream is decomposed into even and odd samples internally by

the processing elements operating at one half of the input CLK

(see elements marked by “†” in Figure 7A). In this mode, the

Data Flow Controller routes data samples input through AIN0-

15 to upper and lower processing legs with a one sample

relative delay. Since a new data sample is clocked into either of

the processing legs at CLK/2, each leg processes a data

stream comprised of every other input sample, and the one

sample relative delay of each leg’s input forces the even

samples to be clocked into one leg while the odd samples are

clocked into the other. The user may choose which sample gets

routed to the upper (even) processing leg by asserting SYNC

Specifically, a sample input on the CLK following the assertion

of SYNC

will be routed to the upper processing leg as shown in

Figure 8. With internal multiplexing, the minimum pipeline delay

on the upper processing leg is 14 CLK’s and the pipeline delay

on the bottom leg is 47 CLK’s. The filtered and decimated data

stream is held on AOUT0-15 for 2 CLK’s.

If external multiplexing is selected (INT/EXT

= 0), a

demultiplex function is required off chip to break the input

data into even and odd sample streams for input through

AIN0-15 and BIN0-15. In this mode, the Data Flow Controller

routes the even and odd sample streams directly to the

following processing elements which are all running at the

input CLK rate. This allows the device to perform decimate

by two filtering on signals sampled at up to twice the

maximum CLK rate of the device (104 MSPS). With external

multiplexing, the minimum pipeline delay through the upper

processing leg is 9 CLK’s and the pipeline delay through the

lower processing leg is 26 CLK’s as shown in Figure 7B. In

this mode, SYNC

has no effect on part operation.

NOTE: For proper operation, the samples demultiplexed

to the AIN0-15 input must precede those input to the

BIN0-15 input in sample order. For example, given a data

sequence x0, x1, x2 and x3, the demultiplex function would

route x0 and x2 to AIN0-15 and x1 and x3 to BIN0-15.

Interpolate By 2 Filter Mode (Mode1-0 = 01)

As with the Decimate by Two mode the concept of operation

for the Interpolate by Two Filter mode is more easily

understood by comparing a 7 tap transversal filter

implementation to the equivalent polyphase implementation.

The transversal implementation is shown in Figure 9.

By inspecting filter outputs in Figure 9, it is seen that the

even indexed outputs are the result of the sum-of-products

for the odd coefficients, and the odd indexed outputs are the

result of the sum-of-products for the even coefficients. This

computational partitioning is evident in the polyphase

implementation shown in Figure 10.

FIGURE 7A. DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INT/EXT = 1)

FIGURE 7B. DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INT/EXT

= 0)

EVEN TAP

FILTER

ODD TAP

FILTER

† GROUP DELAY 19

AIN0-15

AOUT0-15

OEA

† Clocked at CLK/2

† GROUP DELAY 19

†

†††

††

† PIPELINE DELAY 2-35

† PIPELINE DELAY 19

EVEN TAP

FILTER

AIN0-15

AOUT0-15

ODD TAP

FILTER

OEA

BIN0-15

GROUP DELAY 19

PIPELINE DELAY 2-35

GROUP DELAY 19

PIPELINE DELAY 19

012

CLK

SYNC

INPUTS DESIGNATED AS EVEN ARE PROCESSED ON THE UPPER

LEG, INPUTS DESIGNATED AS ODD ARE PROCESSED ON THE

LOWER LEG.

AIN0-15

FIGURE 8. DATA SYNCHRONIZATION WITH PROCESSING

LEGS (INT/EXT

= 1)

EVEN ODD

EVEN

HSP43216

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HSP43216VC-52Z

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Manufacturer:

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Active Filter s W/ANNEAL HALFB & FILER 100 PIN PQFP

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HSP43216VC-52Z

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