6
Switching Specications (R
L
= 20 k:)
Over recommended operating conditions unless otherwise specied:
T
A
= -40° C to +100° C, V
CC
= +4.5 V to 30 V, I
F(on)
= 10 mA to 20 mA, V
F(o)
= -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay
Time to Low
Output Level
t
PHL
30 200 400 ns C
L
= 100 pF I
F(on)
= 10 mA,
V
F(o)
= 0.8 V,
V
CC
= 15.0 V,
V
THLH
= 2.0 V,
V
THHL
= 1.5 V
6, 8-12 8, 9
100 ns C
L
= 10 pF
Propagation Delay
Time to High
Output Level
t
PLH
270 400 550 ns C
L
= 100 pF
130 C
L
= 10 pF
Pulse Width
Distortion
PWD 200 450 ns C
L
= 100 pF 13
Propagation Delay
Dierence Between
Any 2 Parts
t
PLH
-t
PHL
-150 200 450 ns 10
Output High Level
Common Mode
Transient Immunity
|CM
H
| 15 30 kV/PsI
F
= 0 mA,
V
O
> 3.0 V
V
CC
= 15.0 V,
C
L
= 100 pF,
V
CM
= 1500 V
P-P
,
T
A
= 25° C
711
Output Low Level
Common Mode
Transient Immunity
|CM
L
|1530 kV/PsI
F
= 10 mA,
V
O
< 1.0 V
12
*All typical values at 25° C, V
CC
= 15 V.
Notes:
1. Derate linearly above 90° C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90° C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90° C free-air temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90° C free-air temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in per cent is dened as the ratio of output collector current (I
O
) to the forward LED input current (I
F
) times 100.
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
RMS
for 1 second (leakage detection
current limit, I
I-O
≤ 5 PA).
8. Pulse: f = 20 kHz, Duty Cycle = 10%.
9. Use of a 0.1 PF bypass capacitor connected between pins 4 and 6 can improve performance by ltering power supply line noise.
10. The dierence between t
PLH
and t
PHL
between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Specications section.)
11. Common mode transient immunity in a Logic High level is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the
output will remain in a Logic High state (i.e., V
O
> 3.0 V).
12. Common mode transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the
output will remain in a Logic Low state (i.e., V
O
< 1.0 V).
13. Pulse Width Distortion (PWD) is dened as |t
PHL
- t
PLH
| for any given device.