8
IPM Dead Time and Propagation Delay Specications
The HCPL-M456 includes a Propagation Delay Dierence
specication intended to help designers minimize “dead
time” in their power inverter designs. Dead time is the time
period during which both the high and low side power
transistors (Q1 and Q2 in Figure 22) are o. Any overlap in
Q1 and Q2 conduction will result in large currents owing
through the power devices between the high and low
voltage motor rails.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the charac ter is tics of the IPM IGBT gate drive
circuit can be analyzed in the same way) it is important
to know the minimum and maximum turn-on (t
PHL
) and
turn-o (t
PLH
) propagation delay specications, preferably
over the desired operating temperature range.
The limiting case of zero dead time occurs when the input
to Q1 turns o at the same time that the input to Q2 turns
on. This case determines the minimum delay between
LED1 turn-o and LED2 turn-on, which is related to the
worst case optocoupler propaga tion delay waveforms,
as shown in Figure 23. A minimum dead time of zero is
achieved in Figure 23 when the signal to turn on LED2
is delayed by (t
PLH max
- t
PHL min
) from the LED1 turn o.
Note that the propagation delays used to calculate PDD
are taken at equal temperatures since the optocoup lers
under consideration are typically mounted in close prox-
im ity to each other. (Specically, t
PLH max
and t
PHL min
in
the previous equation are not the same as the t
PLH max
and t
PHL min
, over the full operating tempera ture range,
specied in the data sheet.) This delay is the maximum
value for the propagation delay dier ence specication
which is specied at 370 ns for the HCPL-M456 over an
operating tempera ture range of -40° C to 100° C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with
the fastest t
PLH
and another with the slowest t
PHL
are in
the same inverter leg. The maximum dead time in this
case becomes the sum of the spread in the t
PLH
and t
PHL
propagation delays as shown in Figure 24. The maximum
dead time is also equiv alent to the dierence between
the maximum and minimum propagation delay dier-
ence specications. The maximum dead time (due to the
optocoup lers) for the HCPL-M456 is 520 ns (= 370 ns -
(-150 ns)) over an operating temperature range of -40° C
to 100° C.
CMR With The LED O (CMRH)
A high CMR LED drive circuit must keep the LED o (V
F
≤ V
F(OFF)
) during common mode transients. For example,
during a +dV
CM
/dt transient in Figure 18, the current
owing through C
LEDN
is supplied by the parallel combi-
nation of the LED and series resistor. As long as the voltage
developed across the resistor is less than V
F(OFF)
the LED
will remain o and no common mode failure will occur.
Even if the LED momentarily turns on, the 100 pF capacitor
from pins 5-4 will keep the output from dipping below the
threshold. The recommended LED drive circuit (Figure 13)
provides about 10 V of margin between the lowest opto-
coupler output voltage and a 3 V IPM threshold during a
15 kV/Ps transient with V
CM
= 1500 V. Additional margin
can be obtained by adding a diode in parallel with the
resistor, as shown by the dashed line connec tion in Figure
18, to clamp the voltage across the LED below V
F(OFF)
.
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED o during a +dV
CM
/dt transient, it is
not desirable for applications requir ing ultra high CMR
H
performance. Figure 20 is the AC equivalent circuit for
Figure 19 during common mode transients. Essen tially
all the current owing through C
LEDN
during a +dV
CM
/dt
transient must be supplied by the LED. CMR
H
failures can
occur at dv/dt rates where the current through the LED
and C
LEDN
exceeds the input threshold. Figure 21 is an
alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the o state.
