ADV202 Data Sheet
Rev. D | Page 24 of 40
Mnemonic
Pins
Used 121-Lead Package 144-Lead Package I/O Description
HOLD
I External Hold Indication for JDATA Input/Output Stream.
Polarity is programmable in the EDMOD0 register. This pin
is always an input.
FCS0
I Used in DCS-DMA Mode. Chip select for the FIFO assigned
to Channel 0 (asynchronous mode).
DREQ1
1 F10 F10 O Data Request for External DMA Interface. Indicates that
the ADV202 is ready to send/receive data to/from the FIFO
assigned to DMA Channel 1.
FSRQ1
O Used in DCS-DMA Mode. Service request from the FIFO
assigned to Channel 1 (asynchronous mode).
CFG[2] I Boot Mode Configuration. This pin is read on reset to
determine the boot configuration of the on-board
processor. The pin should be tied to IOVDD or DGND
through a 10 kΩ resistor.
DACK1
1 G9 F9 I Data Acknowledge for External DMA Interface. Signal
from the host CPU, which indicates that the data transfer
request (
DREQ1
) has been acknowledged and data
transfer can proceed. This pin must be held high at all
times unless a DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA interface is not
used, even if the DMA channels are disabled.
FCS1
I Used in DCS-DMA Mode. Chip select for the FIFO assigned
to Channel 1 (asynchronous mode).
HDATA[31:28] 4 J2 to J4, H1 K3, J1 to J3 I/O Host Expansion Bus.
JDATA[7:4] I/O JDATA Bus (JDATA Mode).
HDATA[27:24] 4 H2 to H4, G4 J4, H1 to H3 I/O Host Expansion Bus.
JDATA[3:0] I/O JDATA Bus (JDATA Mode).
HDATA[23:16] 8 G3, G2, F4, F3, F2 E2,
E3, E4
H4, G1 to G4, F1 to F3 I/O Host Expansion Bus.
SCOMM[7] 8 L2 M2 I/O When not used, this pin should be tied low via a 10 kΩ
resistor.
SCOMM[6] L3 M3 I/O When not used, this pin should be tied low via a 10 kΩ
resistor.
SCOMM[5] L4 M4 I/O This pin must be used in multiple chip mode to align the
outputs of two or more ADV202s. For details, see the
Applications section and AN-796 ADV202 Multichip
Application application note. When not used, this pin
should be tied low via a 10 kΩ resistor.
SCOMM[4] K1 L1 O LCODE Output in Encode Mode. When LCODE is enabled,
the output on this pin indicates on a high transition that
the last data-word for a field has been read from the FIFO.
For an 8-bit interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled by default.
SCOMM[3] K2 L2 O This pin should be tied low via a 10 kΩ resistor.
SCOMM[2] L5 L3 O This pin should be tied low via a 10 kΩ resistor.
SCOMM[1] K4 K1 I This pin should be tied low via a 10 kΩ resistor.
SCOMM[0] K3 K2 O This pin should be tied low via a 10 kΩ resistor.
VCLK 1 E9 E12 I Video Data Clock. Must be supplied if video data is
input/output on the VDATA bus.
VDATA[11:0] 12 D11, D10, C7, C9,
C10, B7, B8, B9, B11,
B10, A7, A10
D10 to D12,
C10 to C12,
B10 to B12, A9 to A11
I/O Video Data. Unused pins should be pulled down via a
10 kΩ resistor.
VSYNC 1 D8 E10 I/O Vertical Sync for Video Mode.
VFRM Raw Pixel Mode Framing Signal. Indicates first sample of a
tile when asserted high.
HSYNC 1 D9 E11 I/O Horizontal Sync for Video Mode.
VRDY O Raw Pixel Mode Ready Signal.