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ADV202BBCZ-135
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P41
ADV202
Data Sheet
Rev.
D
| P
age
36
of
40
ENCODE/DECODE SDTV
V
IDEO APPLICATION
Fig
ure
27
shows two
ADV202 chip
s using 10
-
bi
t C
CIR656 in normal host mode.
04723-005
ENCODE MODE
32-BI
T
HOS
T CPU
ADV202
HD
AT
A[31:0]
D
AT
A[31:0]
10-BI
T
VIDEO
DECO
DER
IRQ
INTR
ADDR[3:0]
ADDR[3:0]
P[19:
10]
VD
AT
A[
1
1:2]
VID
EO IN
LLC1
VCL
K
MCL
K
CS
CS
RD
RD
WE
WE
ACK
ACK
27MHz
OSC
DECODE MODE
32-BI
T
HOS
T CPU
ADV202
HD
AT
A[31:0]
D
AT
A[31:0]
10-BI
T
VIDEO
ENCO
DER
IRQ
INTR
ADDR[3:0]
ADDR[3:0]
P[9:0]
VD
AT
A[
1
1:2]
VID
EO OUT
CLKI
N
VCL
K
MCL
K
CS
CS
RD
RD
WE
WE
ACK
ACK
Figure
27
. Encode/Deco
de
—
SDTV Video A
pplication
Data Sheet
ADV202
Rev.
D
| P
age
37
of
40
ASIC APPLIC
ATION (32
-
BIT HOST/32
-
BIT ASIC)
Fig
ure
28
shows two
ADV202 chip
s using 10
-
bi
t C
CIR656 in normal host mode.
04723-006
ENCODE MODE
32-BI
T
HOS
T CPU
ADV202
D
AT
A[31:0]
IRQ
IRQ
ADDR[3:0]
ADDR[3:0]
CS
CS
RD
RD
WE
WE
ACK
ACK
ASI
C
10-BI
T
VIDEO
DECO
DER
P[19:
10]
LLC1
VD
AT
A[
1
1:2]
VID
EO IN
VCL
K
MCL
K
DREQ
0
DREQ
0
DACK0
DACK0
HD
AT
A[31:0]
D
AT
A[31:0]
27MHz
OSC
DECODE MODE
31 -BI
T
HOS
T CPU
ADV202
D
AT
A[31:0]
IRQ
IRQ
ADDR[3:0]
ADDR[3:0]
CS
CS
RD
RD
WE
WE
ACK
ACK
ASI
C
10-BI
T
VIDEO
ENCO
DER
P[9:0]
VD
AT
A[
1
1:2]
VID
EO OUT
CLKI
N
VCLK
MCL
K
DREQ
0
DREQ
0
DACK0
DACK0
HD
AT
A[31:0]
D
AT
A[31:0]
Figure
28
. Encode/Deco
de ASIC Applic
atio
n
ADV202
Data Sheet
Rev.
D
| P
age
38
of
40
HIPI (HOST INTER
FACE
—
PIXEL INTER
FACE)
Fig
ure
29
is a typical configuration usin
g H
IPI mode.
04723-007
HD
AT
A<31>
Y0/
G0<M
SB>
HD
AT
A<30>
Y0/
G0<6>
HD
AT
A<29>
Y0/
G0<5>
HD
AT
A<28>
Y0/
G0<4>
HD
AT
A<27>
Y0/
G0<3>
HD
AT
A<26>
Y0/
G0<2>
HD
AT
A<25>
Y0/
G0<1>
HD
AT
A<24>
Y0/
G0<0>
HD
AT
A<23>
Cb0/
G1<
MSB>
HD
AT
A<22>
Cb0/
G1<
6>
HD
AT
A<21>
Cb0/
G1<
5>
HD
AT
A<20>
Cb0/
G1<
4>
HD
AT
A<19>
Cb0/
G1<
3>
HD
AT
A<18>
Cb0/
G1<
2>
HD
AT
A<17>
Cb0/
G1<
1>
HD
AT
A<16>
Cb0/
G1<
0>
HD
AT
A<15>
Y1/
G2<M
SB>
HD
AT
A<14>
Y1/
G2<6>
HD
AT
A<13>
Y1/
G2<5>
HD
AT
A<12>
Y1/
G2<4>
HD
AT
A<
1
1>
Y1/G
2<3>
HD
AT
A<10>
Y1/
G2<2>
HD
AT
A<9>
Y1/
G2<1>
HD
AT
A<8>
Y1/
G2<0>
HD
AT
A<7>
Cr0/G
3<MSB>
HD
AT
A<6>
Cr0/G
3<6>
HD
AT
A<5>
Cr0/G
3<5>
HD
AT
A<4>
Cr0/G
3<4>
HD
AT
A<3>
Cr0/G
3<3>
HD
AT
A<2>
Cr0/G
3<2>
HD
AT
A<1>
Cr0/G
3<1>
HD
AT
A<0>
Cr0/G
3<0>
CS
D
AT
A
[31:
0]
CS
RD
RD
WR
WE
ACK
ACK
IRQ
IRQ
DREQ
DREQ
0
DACK
DACK0
MCL
K
74.25M
Hz
DREQ
DREQ1
DACK
DACK1
32-BI
T HOS
T
RA
W
PIXE
L
D
AT
A
PA
TH
COMPRESSED
D
AT
A
PA
TH
Figure
29
.
Host Interface
—
Pixel Interface M
ode
JDATA INTERFAC
E
Fig
ure
30
sh
ow
s a typical config
uratio
n us
ing JD
A
T
A with a
dedicated JD
A
T
A
ou
tput, 16
-
bit host, and 10
-
b
it CCIR656.
04723-008
16-BI
T
HOS
T CPU
ASI
C
ADV202
HD
AT
A[15:0]
D
AT
A[
15:0]
IRQ
IRQ
ADDR[3:0]
ADDR[3:0]
P[19:
10]
VD
AT
A[
1
1:2]
FIELD
FIELD
VS
VSYNC
HS
LLC1
HSYNC
VCL
K
MCL
K
VID
EO IN
YCrCb
CS
CS
JD
AT
A[7:0]
HOLD
V
ALID
RD
RD
WE
WE
ACK
ACK
Figure
30
. JDATA Applica
tion
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P41
ADV202BBCZ-135
Mfr. #:
Buy ADV202BBCZ-135
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 Video IC 135 MHz
Lifecycle:
New from this manufacturer.
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