13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
TM
32,768 x 18 and 65,536 x 18
PROGRAMMABLE ALMOST-FULL FLAG (
PAFPAF
PAFPAF
PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (32,768-m) writes for the IDT72V275
and (65,536-m) writes for the IDT72V285. The offset “m” is the full offset value.
The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAF will go LOW after (32,769-m) writes for the
IDT72V275 and (65,537-m) writes for the IDT72V285, where m is the full offset
value. The default setting for this value is stated in the footnote of Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAEPAE
PAEPAE
PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in the footnote of Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HFHF
HFHF
HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference
between the write and read pointers becomes less than or equal to half of the
total depth of the device; the rising RCLK edge that accomplishes this condition
sets HF HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 32,768
for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 32,769 for the
IDT72V275 and 65,537 for the IDT72V285.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
