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72V285L10PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
TM
32,768 x 18 and 65,536 x 18
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. D = 32,768
for IDT72V275 and 65,536 for IDT72V285.
5. EF goes HIGH at 60ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
t
REF
t
RTS
t
ENH
4512 drw 14
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
W
1
t
PAF
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
t
RTS
t
ENS
t
ENH
(3)
t
A
t
A
(3)
(5)
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
TM
32,768 x 18 and 65,536 x 18
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. X = 14 for the IDT72V275 and X = 15 for the IDT72V285.
t
REF
t
RTS
t
ENH
4512 drw 15
t
ENS
W
x
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0 - Qn
t
SKEW2
12
1
t
PAF
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
t
RTS
WEN
t
ENS
W
1
t
ENH
(4)
(5)
3
4
t
ENH
W
3
t
A
t
A
WCLK
SEN
SI
4512 drw 16
tENH
t
ENS
tLDS
LD
tDS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
tENH
BIT X
(1)
tLDH
tLDHtLDH
tDH
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
TM
32,768 x 18 and 65,536 x 18
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
In FWFT mode: D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAF
). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
(3)
t
PAF
REN
4512 drw 19
t
ENS
t
ENH
t
ENS
D - (m+1) words in FIFO
(2)
t
PAF
D - m words in FIFO
(2)
t
SKEW2
1
2
12
D-(m+1) words
in FIFO
(2)
RCLK
LD
REN
Q
0
- Q
15
tLDH
tLDS
tENS
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
tENH
tENH
tLDH
4512 drw 18
t
CLK
tA
tA
tCLKH
tCLKL
WCLK
LD
WEN
D
0
- D
15
4512 drw 17
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

72V285L10PFG

Mfr. #:
Buy 72V285L10PFG
Manufacturer:
IDT
Description:
FIFO 3.3V 64K X 18 SUPER SYNC
Lifecycle:
New from this manufacturer.
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