16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
TM
32,768 x 18 and 65,536 x 18
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First word latency: 60ns + tREF + 1*TRCLK.
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising
edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
RCLK
REN
4512 drw 11
EF
t
CLK
t
CLKH
t
CLKL
t
ENH
t
REF
t
A
t
OLZ
t
OE
Q
0
- Q
n
OE
WCLK
(1)
t
SKEW3
WEN
D
0
- D
n
t
ENS
t
ENS
t
ENH
t
DS
t
DHS
D
0
1
2
t
OLZ
NO OPERATION
LAST WORD
D
0
D
1
D
1
t
ENS
t
ENH
t
DS
t
DH
t
OHZ
LAST WORD
t
REF
t
ENH
t
ENS
t
A
t
A
t
REF
t
ENS
t
ENH
D
0
- D
n
WEN
RCLK
REN
tENH
tENH
Q
0
- Q
n
DATA READ
NEXT DATA READDATA IN OUTPUT REGISTER
tSKEW1
(1)
4512 drw 10
WCLK
NO WRITE
1
2
1
2
tDS
NO WRITE
tWFF
tWFF
tWFF
tA
tENS
tENS
tSKEW1
(1)
tDS
tA
D
X
tDH
tCLK
tCLKH
tCLKL
D
X
+1
tWFF
tDH
FF
