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ISL24202IRTZ

P1-P3P4-P6P7-P9P10-P12
ISL24202
4
FN7587.0
March 15, 2011
Absolute Maximum Ratings Thermal Information
Supply Voltage
AV
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Input Voltage with respect to Ground
SET, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
DD
+0.3V
CE and WP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DD
+0.3V
Output Voltage with respect to Ground
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
DD
Continuous Output Current
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical) θ
JA
(°C/W) θ
JC
(°C/W)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . . 53 11
Moisture Sensitivity (see Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Range
AV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: V
DD
= 3.3V, AV
DD
= 18V, R
SET
= 5kΩ, R
1
= 10kΩ, R
2
= 10kΩ, (See Figure 5). Typicals are at
T
A
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
DC CHARACTERISTICS
V
DD
V
DD
Supply Range - Operating 2.25 3.6 V
AV
DD
AV
DD
Supply Range Supporting EEPROM Programming 10.8 19 V
AV
DD
AV
DD
Supply Range for Wide-Supply Operation without
EEPROM Programming
4.5 19 V
I
DD
V
DD
Supply Current CTL = 0.5*V
DD
40 65 µA
I
AVDD
AV
DD
Supply Current CTL = 0.5*V
DD
24 38 µA
OUT PIN CHARACTERISTICS
SET
ZSE
SET Zero-Scale Error ±3LSB
SET
FSE
SET Full-Scale Error ±8LSB
V
OUT
OUT Voltage Range V
SET
+ 1.75 AV
DD
V
SET
VD
SET Voltage Drift 7µV/°C
I
OUT
Maximum OUT Sink Current 4mA
INL Integral Non-Linearity ±2LSB
DNL Differential Non-Linearity ±1LSB
EEPROM CHARACTERISTICS
t
PROG
EEPROM Programming Time (internal) 100 ms
UP/DOWN COUNTER CONTROL INPUTS (SEE FIGURE 11)
V
IH
CE and CTL Input Logic High Threshold 0.7*V
DD
V
V
IL
CE and CTL Input Logic Low Threshold 0.3*V
DD
V
I
CS_PD
CE Input Pull Down Current Sink 0.5 1.5 µA
I
CTL
CTL Input Bias Current CTL = GND (sourcing) 7 15 µA
CTL = V
DD
(sinking) 7 15 µA
t
ST
CE to CTL Start Delay 50 µs
t
READ
EEPROM Recall Time (after CE de-asserted) 10 ms
ISL24202
5
FN7587.0
March 15, 2011
t
H_REJ
CTL High Pulse Rejection Width 20 µs
t
L_REJ
CTL Low Pulse Rejection Width 20 µs
t
H_MIN
CTL High Minimum Valid Pulse Width 200 µs
t
L_MIN
CTL Low Minimum Valid Pulse Width 200 µs
t
MTC
CTL Minimum Time Between Counts 10 µs
V
PROG
CTL EEPROM Program Voltage (see Figure 9) 4.9 19 V
t
PROG
CTL EEPROM Programming Signal Time 200 µs
t
H_PROP
CTL High-to-Mid to OUT Propagation Time 65 µs
t
L_PROP
CTL Low-to-Mid to OUT Propagation Time 65 µs
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications Test Conditions: V
DD
= 3.3V, AV
DD
= 18V, R
SET
= 5kΩ, R
1
= 10kΩ, R
2
= 10kΩ, (See Figure 5). Typicals are at
T
A
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6) UNITS
ISL24202
6
FN7587.0
March 15, 2011
Application Information
LCD panels have a V
COM
(common voltage) that must be precisely
set to minimize flicker. Figure 3 shows a typical V
COM
adjustment
circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24202. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is not needed again - the ISL24202 automatically powers
up with the correct V
COM
voltage programmed previously.
The ISL24202 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (Figure 4) to change the current
drawn at the OUT pin, which then changes the voltage created by
the R
1
- R
2
resistor divider (Figure 5). The OUT voltage can then be
buffered by an external amplifier (A2) to generate a buffered output
voltage (V
COM
) capable of driving the V
COM
input of an LCD panel.
The amount of current sunk is controlled by the setting of the
DCP, which is recalled at power-up from the ISL24202’s internal
EEPROM. The EEPROM is typically programmed during panel
manufacture. As noted in the “Electrical Specifications” section
on page 4, the ISL24202 requires a minimum AV
DD
voltage of
10.8V for EEPROM programming, but will work in normal
operation down to 4.5V after the EEPROM has been
programmed, with no additional EEPROM writing.
DCP (Digitally Controllable Potentiometer)
The DCP controls the voltage that ultimately controls the SET
current. Figure 4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation 1:
Output Current Sink
Figure 5 shows the schematic of the OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor R
SET
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
The external R
SET
resistor sets the full-scale (maximum) sink current
that can be pulled from the OUT node. The relationship between
I
OUT
and Register Value is shown in Equation 2.
The maximum value of I
OUT
can be calculated by substituting the
maximum register value of 255 into Equation 2, resulting in
Equation 3:
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
SET
ISL24202
R
1
R
2
AV
DD
AV
DD
V
COM
I
OUT
V
DD
R
SET
R
A
R
C
AV
DD
V
COM
R
B
R
1
= R
A
R
2
= R
B
+R
C
R
SET
= R
A
R
B
+ R
A
R
C
20R
B
OUT
A2
V
DCP
RegisterValue 1+
256
---------------------------------------------------
⎝⎠
⎛⎞
AV
DD
20
--------------
⎝⎠
⎛⎞
=
(EQ. 1)
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
AV
DD
19R
R
0
1
2
255
254
253
252
251
REGISTER VALUE
AV
DD
20
V
DCP
FIGURE 5. CURRENT SINK CIRCUIT
A
VDD
R
SET
V
DCP
SET
OUT
A
VDD
I
OUT
R
1
R
2
V
SAT
Q1
A1
V
OUT
V
SET
= V
DCP
= I
OUT
* R
SET
I
OUT
I
OUT
V
DCP
R
SET
-------------
RegisterValue 1+
256
---------------------------------------------------
⎝⎠
⎛⎞
AV
DD
20
--------------
⎝⎠
⎛⎞
1
R
SET
-------------
⎝⎠
⎛⎞
==
(EQ. 2)
I
OUT
MAX()
A
VDD
20R
SET
--------------------
=
(EQ. 3)
I
STEP
AV
DD
256()20()R
SET
()
----------------------------------------------
=
(EQ. 4)
P1-P3P4-P6P7-P9P10-P12

ISL24202IRTZ

Mfr. #:
Buy ISL24202IRTZ
Manufacturer:
Renesas / Intersil
Description:
LCD Gamma Buffers ISL24202IRTZFREE VCO M CLBTR W/AN I2C
Lifecycle:
New from this manufacturer.
Delivery:
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