ISL24202
8
FN7587.0
March 15, 2011
Assuming that the I
OUT
(MIN) = 0 instead of I
STEP
, the expression
in Equation 14 simplifies to:
OUT Pin Leakage Current
When the voltage on the OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
I
SET
current. Figure 6 shows the I
SET
current and the OUT pin
current for OUT pin voltage up to 19V. In applications where the
voltage on the OUT pin will be greater than 10V, the actual output
voltage will be lower than the voltage calculated by Equation 8
due to this extra current. The graph in Figure 6 was measured
with R
SET
= 4.99kΩ.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 7. When applying power, V
DD
should be applied before or
at the same time as AV
DD
. The minimum time for t
VS
is 0µs.
When removing power, the sequence of V
DD
and AV
DD
is not
important.
Do not remove V
DD
or AV
DD
within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AV
DD
must be ≥10.8V. If further
programming is not required, the ISL24202 will operate over an
AV
DD
range of 4.5V to 19V.
During EEPROM programming, I
DD
and I
AVDD
will temporarily be
4-5x higher for up to 100ms (t
PROG
).
Up/Down Counter Interface
The ISL24202 allows the adjustment of the output V
COM
voltage
and the programming of the non-volatile memory through a
single pin (CTL) when the CE (counter enable) pin is high. The CTL
pin is biased so that its voltage is set to VDD/2 if the driving
circuit is set to Tri-state or High Impedance (Hi-Z), allowing
up/down operation using common digital I/O logic.
CTL Pin
When a mid-high-mid transition is detected on the CTL pin (see
Figure 11), the internal register value counts down by one at the
trailing (high-mid) edge, and the output V
COM
voltage is
increased according to Equation 8. Similarly, when a mid-low-mid
transition is detected on the CTL pin, the internal register value
counts up by one at the trailing (low-mid) edge, and the output
V
COM
voltage is decreased. Once the maximum or minimum
value is reached, the counter saturates and will not overflow or
underflow beyond those values.
CTL should have a noise filter to reduce bouncing or noise on the
input that could cause unwanted counts when the CE pin is high.
Figure 8 shows a simple debouncing circuit consisting of a series
1kΩ resistor and a shunt 0.01µF capacitor connected on the CTL
pin. To avoid unintentional adjustment, the ISL24202 guarantees
to reject CTL pulses shorter than 20µs.
This pin is pulled above 4.9V to program the EEPROM. See
“Programming the EEPROM” on page 9 for details.
After CE (Counter Enable) is asserted and after programming
EEPROM, the very first CTL pulse is ignored (see Figure 11) to
avoid the possibility of a false count (since CTL state may be
unknown after programming).
CE Pin
To change the counter controlling the output voltage, the CE
(Counter Enable) pin must be pulled high (V
DD
). When the CE pin
is pulled low, the counter value is loaded from EEPROM, which
takes 10ms (during which the inputs should remain constant).
The CE pin has an internal pull-down to keep it at a logic low
V
COM
SPAN
R
1
R⋅
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
AV
DD
20R
SET
--------------------
⎝⎠
⎜⎟
⎛⎞
R
1
R⋅
2
R
1
R
2
+
--------------------
⎝⎠
⎜⎟
⎛⎞
I
DVROUT
MAX()==
(EQ. 15)
FIGURE 6. OUT PIN LEAKAGE CURRENT
02468101214161820
OUT PIN VOLTAGE (V)
CURRENT (mA)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
OUT PIN CURRENT
SET PIN CURRENT
REGISTER = 255
V
DD
A
VDD
t
VS
FIGURE 7. POWER SUPPLY SEQUENCE
FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN
ISL24202
CTL
0.01µF
1kΩ
AV
DD
CLOSE TO
EEPROM
PROGRAM
