73S8009R Data Sheet DS_8009R_056
18 Rev. 1.3
3.9 Chip Select
The CS pin is provided to allow multiple circuits to operate in parallel, driven from the same host control
bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described.
The pins IOUC, AUX1UC, and AUX2UC operate to transfer data to the smart card via IO, AUX1, and
AUX2 when the smart card is activated. IO, AUX1, and AUX2 have 11 KΩ pull-up resistors while OFF
and RDY have 20 KΩ pull-up resistors.
When CS goes low, the states of the pins RSTIN, CMDVCC%, CMDVCC#, and CLKIN are latched and
held internally. The pull-up for pins IOUC, AUX1UC, and AUX2UC become a very weak pull-up of
approximately 3 microamperes. No transfer of data is possible between IOUC, AUX1UC, AUX2UC and
the smart-card signals IO, AUX1, and AUX2. The signals OFF and RDY are set to high impedance and
the internal 20 KΩ pull-up resistors are disconnected. PWRDN is not latched when CS is low.
The operation of the fault sensing circuits and card sense inputs (in regards to de-activation) are not
affected by CS.
CS
OFF, I/OUC, AUX1UC,
AUX2UC
CONTROL SIGNALS
FUNCTIONAL
HI-Z STATE
HI-Z STATE
t
SL
t
DZ
t
IS
t
SI
t
ID
t
DI
Figure 9: CS Timing Definitions
3.10 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the
activation sequencer enables the I/O reception state. See Section 3.6 Activation and Deactivation
Sequence for more details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and
AUX2UC are high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling
edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input
I/O line rising edge is detected, both I/O lines return to their neutral state.
Figure 10 shows the state diagram of how the I/O and I/OUC lines are managed to become input or
output. The delay between the I/O signals is shown in Figure 11.
