73S8009R Data Sheet DS_8009R_056
4 Rev. 1.3
Figures
Figure 1: 73S8009R Block Diagram ......................................................................................................... 2
Figure 2: 73S8009R 20-Pin QFN Pinout
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Figure 3: 73S8009R 28-Pin SO Pinout
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Figure 4: Typical 73S8009R Application Schematic
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Figure 5: Activation Sequence
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Figure 6: Deactivation Sequence
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Figure 7: OFF Activity Outside and Inside a Card Session
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Figure 8: Power-down Operation
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Figure 9: CS Timing Definitions
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Figure 10: I/O and I/OUC State Diagram
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Figure 11: I/O to I/OUC Delay Timing Diagram
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Figure 12: 20-pin QFN Package Dimensions
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Figure 13: 28-Pin SO Package Dimensions
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Tables
Table 1: 73S8009R Pin Definitions .......................................................................................................... 6
Table 2: Absolute Maximum Device Ratings
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Table 3: Recommended Operating Conditions
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Table 4: DC Smart Card Interface Requirements
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Table 5: Digital Signals Characteristics
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Table 6: DC Characteristics
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Table 7: Voltage / Temperature Fault Detection Circuits
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Table 8: Choice of VCC Pin Capacitor
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Table 9: Order Numbers and Packaging Marks
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