1. General description
The PTN3360A is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 2.5 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the
PTN3360A provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 1.1 V on the source side and provides a channel for level
shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V
source-side and 5 V sink-side. The DDC channel is implemented using pass-gate
technology providing level shifting as well as disablement (isolation between source and
sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3360A typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or
HDMI v1.3a specification. By using PTN3360A, chip set vendors are able to implement
such reconfigurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure 1.
The PTN3360A main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of
DisplayPort
Standard v1.1
and/or
PCI Express Standard v1.1
, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The
I
2
C-bus channel level-translates the DDC signals between 3.3 V (source) and 5.0 V (sink).
The PTN3360A is a fully featured HDMI as well as DVI level shifter. It is functionally
equivalent to PTN3300A but provides higher speed performance and higher ESD
robustness. The PTN3360A is also equivalent to PTN3360B with the exception that
PTN3360A provides inverting level shifting on the HPD channel.
PTN3360A is powered from a single 3.3 V power supply consuming a small amount of
power (120 mW typ.) and is offered in a 48-terminal HVQFN48 package.
PTN3360A
Enhanced performance HDMI/DVI level shifter with inverting
HPD
Rev. 02 — 8 October 2009 Product data sheet
PTN3360A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 8 October 2009 2 of 21
NXP Semiconductors
PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1. Typical application system diagram
002aae204
OUT_D1
OUT_D1+
IN_D1
IN_D1+
HPD_SOURCE_N HPD_SINK
SCL_SINK
SDA_SINK
DDC_EN
(0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
OUT_D2
OUT_D2+
IN_D2
IN_D2+
OUT_D3
OUT_D3+
IN_D3
IN_D3+
OUT_D4
OUT_D4+
IN_D4
IN_D4+
PTN3360A
OE_N
DVI CONNECTOR
5 V
5 V
0 V to 5 V
0 V to 1.1 V
3.3 V
3.3 V
3.3 V
AC-coupled
differential pair
clock
CLOCK LANE
DATA LANE
DATA LANE
DATA LANE
AC-coupled
differential pair
TMDS data
AC-coupled
differential pair
TMDS data
AC-coupled
differential pair
TMDS data
TX
TX
FF
TMDS
clock
pattern
MULTI-MODE DISPLAY SOURCE
TX
TX
FF
TMDS
coded
data
TX
TX
FF
TMDS
coded
data
TX
TX
FF
TMDS
coded
data
PCIe PHY ELECTRICAL
CONFIGURATION
DDC I/O
(I
2
C-bus)
PCIe
output buffer
reconfigurable I/Os
PCIe
output buffer
PCIe
output buffer
PCIe
output buffer
PTN3360A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 8 October 2009 3 of 21
NXP Semiconductors
PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
2. Features
2.1 High-speed TMDS level shifting
n Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.3a compliant open-drain current-steering differential output signals
n TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock)
n Integrated 50 termination resistors for self-biasing differential inputs
n Back-current safe outputs to disallow current when device power is off and monitor is
on
n Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
n Integrated DDC level shifting (3.3 V source to 5 V sink side)
n 0 Hz to 400 kHz I
2
C-bus clock frequency
n Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting
n HPD inverting level shift from 0 V on the sink side to 1.1 V on the source side, or from
5 V on the sink side to 0 V on the source side
n Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
n Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General
n Power supply 3.3 V ± 10 %
n ESD resilience to 8 kV HBM, 500 V CDM
n Power-saving modes (using output enable)
n Back-current-safe design on all sink-side main link, DDC and HPD terminals
n Transparent operation: no re-timing or software configuration required
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
PTN3360ABS HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals;
body 7 × 7 × 0.85 mm
SOT619-1

PTN3360ABS,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized AC Coupld HDMI/DVI LVL Shifter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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