PTN3360ABS,518 Datasheet PTN3360ABS,518 | P7-P9

Product data sheet Rev. 02 — 8 October 2009 7 of 21

NXP Semiconductors

PTN3360A

Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD

[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

OUT_D1+ 22 TMDS differential

output

HDMI compliant TMDS output. OUT_D1+ makes a differential pair

with OUT_D1−. OUT_D1+ is in phase with IN_D1+.

OUT_D1− 23 TMDS differential

output

HDMI compliant TMDS output. OUT_D1− makes a differential pair

with OUT_D1+. OUT_D1− is in phase with IN_D1−.

HPD and DDC signals

HPD_SINK 30 5 V CMOS

single-ended input

0 V to 5 V (nominal) input signal. This signal comes from the DVI or

HDMI sink. A HIGH value indicates that the sink is connected; a

LOW value indicates that the sink is disconnected. HPD_SINK is

pulled down by an integrated 200 kΩ pull-down resistor.

HPD_SOURCE_

7 1.1 V CMOS

single-ended output

0 V to 1.1 V (nominal) output signal. This is level-shifted

logic-inverted version of the HPD_SINK signal.

SCL_SOURCE 9 single-ended 3.3 V

open-drain DDC I/O

3.3 V source-side DDC clock I/O. Pulled up by external termination

to 3.3 V.

SDA_SOURCE 8 single-ended 3.3 V

open-drain DDC I/O

3.3 V source-side DDC data I/O. Pulled up by external termination

to 3.3 V.

SCL_SINK 28 single-ended 5 V

open-drain DDC I/O

5 V sink-side DDC clock I/O. Pulled up by external termination to

5V.

SDA_SINK 29 single-ended 5 V

open-drain DDC I/O

5 V sink-side DDC data I/O. Pulled up by external termination to 5 V.

DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.

When DDC_EN = LOW, buffer/level shifter is disabled.

When DDC_EN = HIGH, buffer and level shifter are enabled.

Supply and ground

2, 11, 15,

21, 26, 33,

40, 46

3.3 V DC supply Supply voltage; 3.3 V ± 10 %.

GND

[1]

1, 5, 12,

18, 24, 27,

31, 36, 37,

ground Supply ground. All GND pins must be connected to ground for

proper operation.

Feature control signals

REXT 6 analog I/O Current sense port used to provide an accurate current reference

for the differential outputs OUT_Dx. For best output voltage swing

accuracy, use of a 10 kΩ resistor (1 % tolerance) from this terminal

to GND is recommended. May also be left open-circuit or tied to

either V

or GND. See Section 6.2 for details.

Miscellaneous

n.c. 3, 4, 10,

34, 35

no connection

to the die

Not connected. May be left open-circuit or tied to GND or V

either

directly or via a resistor.

Table 2. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 02 — 8 October 2009 8 of 21

NXP Semiconductors

PTN3360A

Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD

6. Functional description

Refer to Figure 2 “Functional diagram of PTN3360A”.

The PTN3360A level shifts four lanes of low-swing AC-coupled differential input signals to

DVI and HDMI compliant open-drain current-steering differential output signals, up to

2.5 Gbit/s per lane. It has integrated 50 Ω termination resistors for AC-coupled differential

input signals. An enable signal OE_N can be used to turn off the TMDS inputs and

outputs, thereby minimizing power consumption. The TMDS outputs, HPD_SINK input

and DDC_SINK I/Os are back-power safe to disallow current ﬂow from a powered sink

while the PTN3360A is unpowered.

The PTN3360A's DDC channel provides active level shifting and buffering, allowing 3.3 V

source-side termination and 5 V sink-side termination. The sink-side DDC ports are

equipped with a rise time accelerator enabling drive of long cables or high bus

capacitance. This enables the system designer to isolate bus capacitance to meet HDMI

DDC version 1.3a distance speciﬁcation. The PTN3360A offers back-power safe sink-side

I/Os to disallow backdrive current from the DDC clock and data lines when power is off or

when DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.

The PTN3360A also provides voltage translation for the Hot Plug Detect (HPD) signal

from 0 V to 5 V on the sink side, inverting and level-shifting to 1.1V/0 V on the source side.

The PTN3360A does not re-time any data. It contains no state machines except for the

DDC/I

C-bus block. No inputs or outputs of the device are latched or clocked. Because

the PTN3360A acts as a transparent level shifter, no reset is required.

6.1 Enable and disable features

PTN3360A offers different ways to enable or disable functionality, using the Output Enable

(OE_N) and DDC Enable (DDC_EN) inputs. Whenever the PTN3360A is disabled, the

device will be in Standby mode and power consumption will be minimal; otherwise the

PTN3360A will be in Active mode and power consumption will be nominal. These two

inputs each affect the operation of PTN3360A differently: OE_N affects only the TMDS

channels, and DDC_EN affects only the DDC channel. HPD_SINK does not affect either

of the channels. The following sections and truth table describe their detailed operation.

6.1.1 Hot plug detect

The HPD channel of PTN3360A functions as a level-shifting buffer to pass the HPD logic

signal from the display sink device (via input HPD_SINK) on to the display source device

(via output HPD_SOURCE_N).

The output logic state of HPD_SOURCE_N output always follows the inverse logic state of

input HPD_SINK, regardless of whether the device is in Active or Standby mode.

Product data sheet Rev. 02 — 8 October 2009 9 of 21

NXP Semiconductors

PTN3360A

Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD

6.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional. Input termination resistors are enabled and the internal bias circuits are turned

on.

When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a

high-impedance state and drive zero output current. The IN_Dx input buffers are disabled

and IN_Dx termination is disabled. Power consumption is minimized.

Remark: Note that OE_N has no inﬂuence on the HPD_SINK input, HPD_SOURCE_N

output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS

channel.

6.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never change

state during an I

C-bus operation. Note that disabling DDC_EN during a bus operation will

hang the bus, while enabling DDC_EN during bus trafﬁc would corrupt the I

C-bus

operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I

C-bus

speciﬁcation).

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PTN3360ABS,518

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PTN3360ABS,518