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PTN3360ABS,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
PTN3360A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 8 October 2009 13 of 21
NXP Semiconductors
PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
9. Characteristics
9.1 Differential inputs
[1] UI (unit interval) = t
bit
(bit time).
[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 2.5 Gbit/s per lane. Nominal UI at 2.5 Gbit/s = 400 ps.
360 ps = 400 ps − 10 %.
[3] V
RX_DIFFp-p
= 2 ×|V
RX_D+
− V
RX_D−
|. Applies to IN_Dx signals.
[4] V
i(cm)M(AC)
= |V
RX_D+
+V
RX_D−
| /2− V
RX(cm)
.
V
RX(cm)
= DC (avg) of |V
RX_D+
+V
RX_D−
| /2.
[5] Intended to limit power-up stress on chip set’s PCIe output buffers.
[6] Differential inputs will switch to a high-impedance state when OE_N is LOW.
Table 7. Differential input characteristics for IN_Dx signals
Symbol Parameter Conditions Min Typ Max Unit
UI unit interval
[1] [2]
360 - 4000 ps
V
RX_DIFFp-p
differential input peak-to-peak voltage
[3]
0.175 - 1.200 V
T
RX_EYE
receiver eye time minimum eye width at
IN_Dx input pair
0.8 - - UI
V
i(cm)M(AC)
peak common-mode input voltage (AC) includes all frequencies
above 30 kHz
[4]
- - 100 mV
Z
RX_DC
DC input impedance 40 50 60 Ω
V
RX(bias)
bias receiver voltage
[5]
1.0 1.2 1.4 V
Z
I(se)
single-ended input impedance inputs in
high-impedance state
[6]
100 - - kΩ
PTN3360A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 8 October 2009 14 of 21
NXP Semiconductors
PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
9.2 Differential outputs
The level shifter’s differential outputs are designed to meet HDMI version 1.3 and
DVI version 1.0 specifications.
[1] V
TT
is the DC termination voltage in the HDMI or DVI sink. V
TT
is nominally 3.3 V.
[2] The open-drain output pulls down from V
TT
.
[3] Swing down from TMDS termination voltage (3.3 V ± 10 %).
[4] Maximum rise/fall time at 2.5 Gbit/s = 400 ps. 360 ps = 400 ps − 10 %.
[5] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D− paired input pins.
[6] This lane-to-lane skew budget is in addition to skew between differential input pairs.
[7] Jitter budget for differential signals as they pass through the level shifter.
Table 8. Differential output characteristics for OUT_Dx signals
Symbol Parameter Conditions Min Typ Max Unit
V
OH(se)
single-ended HIGH-level
output voltage
[1]
V
TT
− 0.01 V
TT
V
TT
+ 0.01 V
V
OL(se)
single-ended LOW-level
output voltage
[2]
V
TT
− 0.60 V
TT
− 0.50 V
TT
− 0.40 V
∆V
O(se)
single-ended output
voltage variation
logic 1 and logic 0 state applied
respectively to differential inputs
IN_Dn; R
ref(ext)
connected;
see
Table 5
[3]
400 500 600 mV
I
OZ
OFF-state output current single-ended - - 10 µA
t
r
rise time 20 % to 80 %
[4]
75 - 160 ps
t
f
fall time 80 % to 20 %
[4]
75 - 160 ps
t
sk
skew time intra-pair
[5]
- - 10 ps
inter-pair
[6]
- - 250 ps
t
jit
jitter time jitter contribution
[7]
- - 7.4 ps
PTN3360A_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 8 October 2009 15 of 21
NXP Semiconductors
PTN3360A
Enhanced HDMI/DVI level shifter with inverting 1.1 V HPD
9.3 HPD_SINK input, HPD_SOURCE_N output
[1] Low-speed input changes state on cable plug/unplug.
[2] Measured with HPD_SINK at V
IH
maximum and V
IL
minimum.
[3] Time from HPD_SINK changing state to HPD_SOURCE_N changing state. Includes HPD_SOURCE_N rise/fall time.
[4] Time required to transition from V
OH
to V
OL
or from V
OL
to V
OH
.
[5] Guarantees HPD_SINK is LOW when no display is plugged in.
9.4 OE_N, DDC_EN inputs
[1] Measured with input at V
IH
maximum and V
IL
minimum.
9.5 DDC characteristics
Table 9. HPD characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage HPD_SINK
[1]
2.0 5.0 5.3 V
V
IL
LOW-level input voltage HPD_SINK 0 - 0.8 V
I
LI
input leakage current HPD_SINK
[2]
--10µA
V
OH
HIGH-level output voltage HPD_SOURCE_N; I
OH
= 100 µA;
HPD_SINK = LOW
0.7 - 1.1 V
V
OL
LOW-level output voltage HPD_SOURCE_N; I
OH
= 100 µA;
HPD_SINK = HIGH
0 - 0.2 V
t
PD
propagation delay from HPD_SINK to HPD_SOURCE_N;
50 % to 50 %; C
L
=10pF
[3]
- - 200 ns
t
t
transition time HPD_SOURCE_N rise/fall;
10%to90%; C
L
=10pF
[4]
1 - 20 ns
R
pd
pull-down resistance HPD_SINK input pull-down resistor
[5]
100 200 300 kΩ
Table 10. OE_N, DDC_EN and DDET input characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage 2.0 - - V
V
IL
LOW-level input voltage - - 0.8 V
I
LI
input leakage current OE_N pin
[1]
--10µA
Table 11. DDC characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
clk
clock frequency SCL_SOURCE, SDA_SOURCE, SCL_SINK,
SDA_SINK
- - 400 kHz
ON state (DDC_EN = HIGH)
R
ON
ON resistance pass gate in ON state; I
O
= 15 mA; V
O
= 0.4 V - 7 30 Ω
V
O(sw)
switch output voltage source side; V
I
= 3.3 V; I
O
= −100 µA 1.7 2.1 2.5 V
sink side; V
I
= 5.0 V; I
O
= −100 µA 1.7 2.1 2.5 V
C
io
input/output capacitance V
I
= 3.3 V - 5 10 pF
OFF state (DDC_EN = LOW)
I
LI
input leakage current source side; 0 V < V
I
< 3.3 V −10 - +10 µA
sink side; 0 V < V
I
< 5.0 V −10 - +10 µA
C
io
input/output capacitance V
I
= 3.3 V - 1 5 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

PTN3360ABS,518

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Buy PTN3360ABS,518
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized AC Coupld HDMI/DVI LVL Shifter
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New from this manufacturer.
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