LTC1850IFW#TRPBF Datasheet LTC1851IFW#PBF, LTC1850IFW#PBF, LTC1850CFW#TRPBF | P10-P12

LTC1850/LTC1851

18501f

PI FU CTIO S

CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can

be used single ended relative to the analog input common

pin (COM) or differentially in pairs (CH0 and CH1, CH2 and

CH3, CH4 and CH5, CH6 and CH7).

COM (Pin 9): Analog Input Common Pin. For single-ended

operation (DIFF = 0), COM is the “–” analog input. COM is

disabled when DIFF is high.

REFOUT (Pin 10): Internal 2.5V Reference Output. Re-

quires bypass to analog ground plane with 1µF.

REFIN (Pin 11): Reference Mode Select/Reference Buffer

Input. REFIN selects the Reference mode and acts as the

reference buffer Input. REFIN tied to ground will produce

2.048V on the REFCOMP pin. REFIN tied to the positive

supply disables the reference buffer to allow REFCOMP to

be driven externally. For voltages between 1V and 2.6V,

the reference buffer produces an output voltage on the

REFCOMP pin equal to 1.6384 times the voltage on REFIN

(4.096V on REFCOMP for a 2.5V input on REFIN).

REFCOMP (Pin 12): Reference Buffer Output. REFCOMP

sets the full-scale input span. The reference buffer pro-

duces an output voltage on the REFCOMP pin equal to

1.6384 times the voltage on the REFIN pin (4.096V on

REFCOMP for a 2.5V input on REFIN). REFIN tied to

ground will produce 2.048V on the REFCOMP pin.

REFCOMP can be driven externally if REFIN is tied to the

positive supply. Requires bypass to analog ground plane

with 10µF tantalum in parallel with 0.1µF ceramic or 10µF

ceramic.

GND (Pin 13): Ground. Tie to analog ground plane.

(Pin 14): 5V Supply. Short to Pin 15.

(Pin 15): 5V Supply. Bypass to GND with 10µF

tantalum in parallel with 0.1µF ceramic or 10µF ceramic.

GND (Pin 16): Ground for Internal Logic. Tie to analog

ground plane.

DIFF

OUT

/S6 (Pin 17): Three-State Digital Data Output.

Active when RD is low. Following a conversion, the single-

ended/differential bit of the present conversion is available

on this pin concurrent with the conversion result. In

Readback mode, the single-ended/differential bit of the

current sequencer location (S6) is available on this pin.

The output swings between OV

and OGND.

OUT

/S5, A1

OUT

/S4, A0

OUT

/S3 (Pins 18 to 20): Three-

State Digital MUX Address Outputs. Active when RD is

low. Following a conversion, the MUX address of the

present conversion is available on these pins concurrent

with the conversion result. In Readback mode, the MUX

address of the current sequencer location (S5-S3) is

available on these pins. The outputs swing between OV

and OGND.

D9/S2 (Pin 21, LTC1850): Three-State Digital Data Out-

put. Active when RD is low. Following a conversion, bit 9

of the present conversion is available on this pin. In

Readback mode, the unipolar/bipolar bit of the current

sequencer location (S2) is available on this pin. The output

swings between OV

and OGND.

D11/S2 (Pin 21, LTC1851): Three-State Digital Data Out-

put. Active when RD is low. Following a conversion, bit 11

of the present conversion is available on this pin. In

Readback mode, the unipolar/bipolar bit of the current

sequencer location (S2) is available on this pin. The output

swings between OV

and OGND.

D8/S1 (Pin 22, LTC1850): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 8

of the present conversion is available on this pin. In

Readback mode, the gain bit of the current sequencer

location (S1) is available on this pin. The output swings

between OV

and OGND.

D10/S1 (Pin 22, LTC1851): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 10

of the present conversion is available on this pin. In

Readback mode, the gain bit of the current sequencer

location (S1) is available on this pin. The output swings

between OV

and OGND.

D7/S0 (Pin 23, LTC1850): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 7

of the present conversion is available on this pin. In

Readback mode, the end of sequence bit of the current

sequencer location (S0) is available on this pin. The output

swings between OV

and OGND.

LTC1850/LTC1851

18501f

D9/S0 (Pin 23, LTC1851): Three-State Digital Data Out-

puts. Active when RD is low. Following a conversion, bit 9

of the present conversion is available on this pin. In

Readback mode, the end of sequence bit of the current

sequencer location (S0) is available on this pin. The output

swings between OV

and OGND.

D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital

Data Outputs. Active when RD is low. The outputs swing

between OV

and OGND.

D8 to D0 (Pins 24 to 32, LTC1851): Three-State Digital

Data Outputs. Active when RD is low. The outputs swing

between OV

and OGND.

NC (Pins 31, 32, LTC1850): No Connect. There is no

internal connection to these pins.

BUSY (Pin 33): Converter Busy Output. The BUSY output

has two functions. At the start of a conversion, BUSY will

go low and remain low until the conversion is completed.

The rising edge may be used to latch the output data. BUSY

will also go low while the part is in Program/Readback

mode (M1 high, M0 low) and remain low until M0 is

brought back high. The output swings between OV

and

OGND.

OGND (Pin 34): Digital Data Output Ground. Tie to analog

ground plane. May be tied to logic ground if desired.

(Pin 35): Digital Data Output Supply. Normally tied

to 5V, can be used to interface with 3V digital logic. Bypass

to OGND with 10µF tantalum in parallel with 0.1µF ceramic

or 10µF ceramic. See Table 5.

M0 (Pin 36): Mode Select Pin 0. Used in conjunction with

M1 to select operating mode. See Table 5

PGA (Pin 37): Gain Select Input. A high logic level selects

gain = 1, a low logic level selects gain = 2.

PI FU CTIO S

UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low

selects a unipolar input span, a high logic level selects a

bipolar input span.

A0 to A2 (Pins 39 to 41): MUX Address Input Pins.

DIFF (Pin 42): Single-Ended/Differential Select Input. A

low logic level selects single-ended mode, a high logic

level selects differential mode.

WR (Pin 43): Write Input. In Direct Address mode, WR low

enables the MUX address and configuration input pins

(Pins 37 to 42). WR can be tied low or the rising edge of

WR can be used to latch the data. In Program mode, WR

is used to program the sequencer. WR low enables the

MUX address and configuration input pins (Pins 37 to 42).

The rising edge of WR latches the data and increments the

counter to the next sequencer location.

RD (Pin 44): Read Input. During normal operation, RD

enables the output drivers when CS is low. In Readback

mode (M1 high, M0 low), RD going low reads the current

sequencer location, RD high advances to the next sequencer

location.

CONVST (Pin 45): Conversion Start Input. This active low

signal starts a conversion on its falling edge.

CS (Pin 46): Chip Select Input. The chip select input must

be low for the ADC to recognize the CONVST and RD

inputs. If SHDN is low, a low logic level on CS selects Nap

mode; a high logic level on CS selects Sleep mode.

SHDN (Pin 47): Power Shutdown Input. A low logic level

will invoke the Shutdown mode selected by the CS pin. CS

low selects Nap mode, CS high selects Sleep mode. Tie

high if unused.

M1 (Pin 48): Mode Select Pin 1. Used in conjunction with

M0 to select operating mode.

LTC1850/LTC1851

18501f

PI FU CTIO S

NOMINAL (V) ABSOLUTE MAXIMUM (V)

PIN NAME DESCRIPTION MIN TYP MAX MIN MAX

1 to 8 CH0 to CH7 Analog Inputs 0 V

–0.3 V

+ 0.3

9 COM Analog Input Common Pin 0 V

–0.3 V

+ 0.3

10 REFOUT 2.5V Reference Output 2.5 – 0.3 V

+ 0.3

11 REFIN Reference Buffer Input 0 2.5 V

–0.3 V

+ 0.3

12 REFCOMP Reference Buffer Output 4.096 –0.3 V

+ 0.3

13 GND Ground, Substrate Ground 0 –0.3 V

+ 0.3

14 V

Supply 4.75 5 5.25 –0.3 6

15 V

Supply 4.75 5 5.25 –0.3 6

16 GND Ground 0 –0.3 V

+ 0.3

17 DIFF

OUT

/S6 Single-Ended/Differential Output OGND OV

–0.3 V

+ 0.3

18 A2

OUT

/S5 MUX Address Output OGND OV

–0.3 V

+ 0.3

19 A1

OUT

/S4 MUX Address Output OGND OV

–0.3 V

+ 0.3

20 A0

OUT

/S3 MUX Address Output OGND OV

–0.3 V

+ 0.3

21 D9/S2 (LTC1850) Data Output OGND OV

–0.3 V

+ 0.3

21 D11/S2 (LTC1851) Data Output OGND OV

–0.3 V

+ 0.3

22 D8/S1 (LTC1850) Data Output OGND OV

–0.3 V

+ 0.3

22 D10/S1 (LTC1851) Data Output OGND OV

–0.3 V

+ 0.3

23 D7/S0 (LTC1850) Data Output OGND OV

–0.3 V

+ 0.3

23 D9/S0 (LTC1851) Data Output OGND OV

–0.3 V

+ 0.3

24 to 30 D6 to D0 (LTC1850) Data Outputs OGND OV

–0.3 V

+ 0.3

24 to 32 D8 to D0 (LTC1851) Data Outputs OGND OV

–0.3 V

+ 0.3

31 to 32 NC (LTC1850)

33 BUSY Converter Busy Output OGND OV

–0.3 V

+ 0.3

34 OGND Output Ground 0 –0.3 V

+ 0.3

35 OV

Output Supply 2.7 5 5.25 –0.3 6

36 M0 Mode Select Pin 0 0 V

–0.3 10

37 PGA Gain Select Input 0 V

–0.3 10

38 UNI/BIP Unipolar/Bipolar Input 0 V

–0.3 10

39 to 41 A0 to A2 MUX Address Inputs 0 V

–0.3 10

42 DIFF Single-Ended/Differential Input 0 V

–0.3 10

43 WR Write Input, Active Low 0 V

–0.3 10

44 RD Read Input, Active Low 0 V

–0.3 10

45 CONVST Conversion Start Input, Active Low 0 V

–0.3 10

46 CS Chip Select Input, Active Low 0 V

–0.3 10

47 SHDN Shutdown Input, Active Low 0 V

–0.3 10

48 M1 Mode Select Pin 1 0 V

–0.3 10

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LTC1850IFW#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 10-bit, 8-ch. Parallel 1.25Msps ADC

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LTC1850IFW#TRPBF

LTC1850IFW#TRPBF

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