LTC1850IFW#TRPBF Datasheet LTC1851IFW#PBF, LTC1850IFW#PBF, LTC1850CFW#TRPBF | P13-P15

LTC1850/LTC1851

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The LTC1850/LTC1851 are complete and very flexible data

acquisition systems. They consist of a 10-bit/12-bit,

1.25Msps capacitive successive approximation A/D con-

verter with a wideband sample-and-hold, a configurable

8-channel analog input multiplexer, an internal reference

and reference buffer amplifier, a 16-bit parallel digital

output and digital control logic including a programmable

sequencer.

CONVERSION DETAILS

he core analog-to-digital converter in the LTC1850/

LTC1851 uses a successive approximation algorithm and

an internal sample-and-hold circuit to convert an analog

signal to a 10-bit/12-bit parallel output. Conversion start

is controlled by the CS and CONVST inputs. At the start of

the conversion, the successive approximation register

(SAR) is reset. Once a conversion cycle is begun, it cannot

be restarted. During the conversion, the internal differen-

tial 10-bit/12-bit capacitive DAC output is sequenced by

the SAR from the most significant bit (MSB) to the least

significant bit (LSB). The outputs of the analog input

multiplexer are connected to the sample-and-hold ca-

pacitors (C

SAMPLE

) during the acquire phase and the

comparator offset is nulled by the zeroing switches. In

this acquire phase, a minimum delay of 150ns will provide

enough time for the sample-and-hold capacitors to ac-

quire the analog signal. During the convert phase, the

comparator zeroing switches are open, putting the com-

parator into compare mode. The input switches connect

SAMPLE

to ground, transferring the differential analog

input charge onto the summing junction. This input

charge is successively compared with the binary weighted

charges supplied by the differential ca

pacitive DAC. Bit

decisions are made by the high speed comparator. At the

end of the conversion, the differential DAC output bal-

ances the input charges. The SAR contents (a 10-bit/

12-bit data word), which represents the difference of the

analog input multiplexer outputs, and the 4-bit address

word are loaded into the 14-bit/16-bit output latches.

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band limited

to frequencies above DC to below half the sampling

frequency. The effective number of bits (ENOBs) is a

measurement of the resolution of an ADC and is directly

related to the S/(N + D) by the equation:

ENOB = [S/(N + D) – 1.76]/6.02

where ENOB is the effective number of bits and S/(N + D)

is expressed in dB. At the maximum sampling rate of

1.25MHz, the LTC1850/LTC1851 maintain near ideal

ENOBs up to and beyond the Nyquist input frequency of

625kHz.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all

harmonics of the input signal to the fundamental itself. The

out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency. THD is

expressed as:

THD Log

VVV Vn

+++

234

222 2

...

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

second through nth harmonics. The LTC1850/LTC1851

have good distortion performance up to the Nyquist fre-

quency and beyond.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD.

IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

LTC1850/LTC1851

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If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at the sum and differ-

ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,

etc.

For example, the 2nd order IMD terms include (fa ± fb).

If the two input sine waves are equal in magnitude, the

value (in decibels) of the 2nd order IMD products can be

expressed by the following formula:

IMD fa fb Log

Amplitude at fa fb

Amplitude at fa

()

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec-

tral component excluding the input signal and DC.

This

value is expressed in decibels relative to the RMS value of

a full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is

reduced by 3dB for a full-scale input signal.

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 68dB for the LTC1851 (11

effective bits) or 56dB for the LTC1850 (9 effective bits).

The LTC1850/LTC1851 have been designed to optimize

input bandwidth, allowing the ADC to undersample input

signals with frequencies above the converter’s Nyquist

frequency. The noise floor stays very low at high frequen-

cies; S/(N + D) becomes dominated by distortion at

frequencies far beyond Nyquist.

ANALOG INPUT MULTIPLEXER

The analog input multiplexer is controlled using the single-

ended/differential pin (DIFF), three MUX address pins (A2,

A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain

select pin (PGA). The single-ended/differential pin (DIFF)

allows the user to configure the MUX as eight single-

ended channels relative to the analog input common pin

(COM) when DIFF is low or as four differential pairs (CH0

and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when

DIFF is high. The channels (and polarity in the differential

case) are selected using the MUX address inputs as shown

in Table 1. Unused inputs (including the COM in the

differential case) should be grounded to prevent noise

coupling.

Table 1. Multiplexer Address Table

MUX ADDRESS SINGLE-ENDED CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0000+ –

0001 + –

0010 + –

0011 + –

0100 + –

0101 + –

0110 + –

0111 + –

MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION

DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

1000+ – *

1001– + *

1010 + – *

1011 – + *

1100 + – *

1101 – + *

1110 + – *

1111 – + *

*Not used in differential mode. Connect to GND.

In addition to selecting the MUX channel, the

LTC1850/

LTC1851 also allows the user to select between two gains

and unipolar or bipolar inputs for a total of four input

spans. PGA high selects a gain of 1 (the input span is equal

to the voltage on REFCOMP). PGA low selects a gain of 2

where the input span is equal to half of the voltage on

REFCOMP. UNI/BIP low selects a unipolar input span,

UNI/BIP high selects a bipolar input span. Table 2 summa-

rizes the possible input spans.

LTC1850/LTC1851

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Table 2. Input Span Table

INPUT SPAN

UNI/BIP PGA REFCOMP = 4.096V

0 0 0 – REFCOMP/2 0 – 2.048V

0 1 0 – REFCOMP 0 – 4.096V

10±REFCOMP/4 ±1.024V

11±REFCOMP/2 ±2.048V

It should be noted that the bipolar input span of the

LTC1850/LTC1851 does not allow negative inputs with

respect to ground. The LTC1850/LTC1851 have a unique

differential sample-and-hold circuit that allows rail-to-rail

inputs.

The ADC will always convert the difference of the

“+” and “–” inputs independent of the common mode

voltage.

The common mode rejection holds up to high

frequencies.

The only requirement is that both inputs can

not exceed the V

power supply voltage or ground. When

a bipolar input span is selected the “+” input can swing

±full scale relative to the “–” input but neither input can

exceed V

or go below ground.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) are

independent of the common mode

voltage, however, the bipolar zero error (BZE) will vary.

The change in BZE is typically less than 0.1% of the

common mode voltage.

Some AC applications may have their performance lim-

ited by distortion. The ADC and many other circuits exhibit

higher distortion when signals approach the supply or

ground. THD will degrade as the inputs approach either

power supply rail. Distortion can be reduced by reducing

the signal amplitude and keeping the common mode

voltage at approximately midsupply.

Driving the Analog Inputs

The inputs of the

LTC1850/

LTC1851 are easy to drive.

Each of the analog inputs can be used as a single-ended

input relative to the input common pin (CH0-COM, CH1-

COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4

and CH5, CH6 and CH7) for differential inputs. Regardless

of the MUX configuration, the “+” and “–” inputs are

sampled at the same instant. Any unwanted signal that is

common mode to both inputs will be reduced by the

common mode rejection of the sample-and-hold circuit.

The inputs draw only one small current spike while charg-

ing the sample-and-hold capacitors at the end of conver-

sion.

During conversion, the analog inputs draw only a

small leakage current.

If the source impedance of the

driving circuit is low, then the

LTC1850/

LTC1851 inputs

can be driven directly.

As source impedance increases, so

will acquisition time.

For minimum acquisition time with

high source impedance, a buffer amplifier should be used.

The only requirement is that the amplifier driving the

analog input(s) must settle after the small current spike

before the next conversion starts (settling time must be

150ns for full throughput rate).

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain of

+1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz should be less than 100Ω.

The second requirement is that the closed-loop bandwidth

must be greater than 20MHz to ensure adequate small-

signal settling for full throughput rate. The following list is

a summary of the op amps that are suitable for driving the

LTC1850/

LTC1851, more detailed information is available

in the Linear Technology Databooks, the LinearView

CD-ROM and on our web site at www.linear-tech.com.

1360: 50MHz Voltage Feedback Amplifier. ±2.5V to

±15V supplies. 5mA supply current. Low distortion.

LT1363: 70MHz Voltage Feedback Amplifier. ±2.5V to

±15V supplies. 7.5mA supply current. Low distortion.

LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback

Amplifiers. ±2.5V to ±15V supplies. 7.5mA supply current

per amplifier. Low distortion.

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LTC1850IFW#TRPBF

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 10-bit, 8-ch. Parallel 1.25Msps ADC

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