Rev B 7/2/15 3 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY
8402015 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1V
DDO_REF
Power Output supply pin for REF_OUT output.
2 REF_OUT Output Reference clock output. LVCMOS/LVTTL interface levels.
3, 4, 13, 16,
25, 32
GND Power Power supply ground.
5, 6, 7 QA0, QA1, QA2 Output Single-ended Bank A clock outputs.LVCMOS/LVTTL interface levels.
8V
DDO_A
Power Power output supply pin for Bank A LVCMOS outputs.
9V
DDO_B
Power Power output supply pin for Bank B LVCMOS outputs.
10, 11, 12 QB0, QB1, QB2 Output Single-ended Bank B clock outputs.LVCMOS/LVTTL interface levels.
14 MR Input Pulldown
Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled
LOW, and LVDS outputs are pulled LOW and HIGH (QCx pulled LOW, nQCx
pulled HIGH). LVCMOS/LVTTL interface levels.
15 V
DD
Power Core supply pin.
17, 24 V
DDO_C
Power Power output supply pin for Bank C LVDS outputs.
18, 19 QC0, nQC0 Output Differential Bank C clock outputs. LVDS interface levels.
20, 21 QC1, nQC1 Output Differential Bank C clock outputs. LVDS interface levels.
22, 23 QC2, nQC2 Output Differential Bank C clock outputs. LVDS interface levels.
26 V
DDA
Power Analog supply pin.
27, 29 OE0, OE2 Input Pulldown
Output enable and configuration pins. See Table 3.
LVCMOS/LVTTL interface levels.
28 OE1 Input Pullup
Output enable and configuration pin. See Table 3.
LVCMOS/LVTTL interface levels.
30, 31
XTAL_IN,
XTAL_OUT
Input Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation
Capacitance (per output)
V
DD
, V
DDO_A,
V
DDO_B,
V
DDO_C
= 3.465V 15 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output
Impedance
QA[0:2],
QB[0:2],
REF_OUT
20
