SPD EEPROM Operation
DDR4 SDRAM modules incorporate serial presence detect (SPD). The SPD data is stor-
ed in a 512-byte JEDEC JC-42.4-compliant EEPROM that is segregated into four 128-
byte, write-protectable blocks. The SPD content is aligned with these blocks as shown in
the table below.
Block Range Description
0 0–127 000h–07Fh Configuration and DRAM parameters
1 128–255 080h–0FFh Module-specific parameters
2 256–319 100h–13Fh Reserved; all bytes coded as 00h
320–383 140h–17Fh Manufacturing information
3 384–511 180h–1FFh End-user programmable
The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,
"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining
128 bytes of storage are available for use by the customer.
The EEPROM resides on a two-wire I
2
C serial interface and is not integrated with the
memory bus in any way. It operates as a slave device in the I
2
C bus protocol, with all
operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achieva-
ble at 2.5V (NOM).
Micron implements reversible software write protection on DDR4 SDRAM-based mod-
ules. This prevents the lower 384 bytes (bytes 0–383) from being inadvertently program-
med or corrupted. The upper 128 bytes remain available for customer use and unpro-
tected.
16GB (x64, DR) 288-Pin DDR4 UDIMM
SPD EEPROM Operation
PDF: CCMTD-1725822587-9883
atf16c2gx64az.pdf – Rev. E 5/17EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 9: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
V
DD
V
DD
supply voltage relative to V
SS
–0.4 1.5 V 1
V
DDQ
V
DDQ
supply voltage relative to V
SS
–0.4 1.5 V 1
V
PP
Voltage on V
PP
pin relative to V
SS
–0.4 3.0 V 2
V
IN
, V
OUT
Voltage on any pin relative to V
SS
–0.4 1.5 V
Table 10: Operating Conditions
Symbol Parameter Min Nom Max Units Notes
V
DD
V
DD
supply voltage 1.14 1.2 1.26 V 1
V
PP
DRAM activating power supply 2.375 2.5 2.75 V 2
V
REFCA(DC)
Input reference voltage command/
address bus
0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V 3
I
VTT
Termination reference current from V
TT
–750 750 mA
V
TT
Termination reference voltage (DC) –
command/address bus
0.49 × V
DD
-
20mV
0.5 × V
DD
0.51 × V
DD
+
20mV
V 4
I
IN
Input leakage current; any input excluding ZQ;
0V < V
IN
< 1.1V
–2.0 2.0 µA 5
I
I/O
DQ leakage; 0V < V
in
< V
DD
–4.0 4.0 µA 5
I
ZQ
Input leakage current; ZQ –3.0 3.0 µA 5, 6
I
OZpd
Output leakage current; V
OUT
= V
DD
; DQ is disabled 5.0 µA
I
OZpu
Output leakage current; V
OUT
=V
SS
; DQ and ODT are
disabled; ODT is disabled with ODT input HIGH
5.0 µA
I
VREFCA
V
REFCA
leakage; V
REFCA
= V
DD
/2 (after DRAM is ini-
tialized)
–2.0 2.0 µA 5
Notes:
1. V
DDQ
tracks with V
DD
; V
DDQ
and V
DD
are tied together.
2. V
PP
must be greater than or equal to V
DD
at all times.
3. V
REFCA
must not be greater than 0.6 x V
DD
. When V
DD
is less than 500mV, V
REF
may be
less than or equal to 300mV.
4. V
TT
termination voltages in excess of the specification limit adversely affect the voltage
margins of command and address signals and reduce timing margins.
5. Multiply by the number of DRAM die on the module.
6. Tied to ground. Not connected to edge connector.
16GB (x64, DR) 288-Pin DDR4 UDIMM
Electrical Specifications
PDF: CCMTD-1725822587-9883
atf16c2gx64az.pdf – Rev. E 5/17EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Table 11: Thermal Characteristics
Symbol Parameter/Condition Value Units Notes
T
C
Commercial operating case temperature 0 to 85 °C 1, 2, 3
T
C
>85 to 95 °C 1, 2, 3, 4
T
OPER
Normal operating temperature range 0 to 85 °C 5, 7
T
OPER
Extended temperature operating range (optional) >85 to 95 °C 5, 7
T
STG
Non-operating storage temperature –55 to 100 °C 6
RH
STG
Non-operating Storage Relative Humidity (non-condensing) 5 to 95 %
NA Change Rate of Storage Temperature 20 °C/hour
Notes:
1. Maximum operating case temperature; T
C
is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum T
C
during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T
C
dur-
ing operation.
4. If T
C
exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate.
5. The refresh rate must double when 85°C < T
OPER
95°C.
6. Storage temperature is defined as the temperature of the top/center of the DRAM and
does not reflect the storage temperatures of shipping trays.
7. For additional information, refer to technical note TN-00-08: "Thermal Applications"
available at micron.com.
16GB (x64, DR) 288-Pin DDR4 UDIMM
Electrical Specifications
PDF: CCMTD-1725822587-9883
atf16c2gx64az.pdf – Rev. E 5/17EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.

MTA16ATF2G64AZ-2G3A1

Mfr. #:
Manufacturer:
Micron
Description:
IC SDRAM DDR4 BGA
Lifecycle:
New from this manufacturer.
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