1. General description
The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a
direction control input (DIR) and dual supply pins (V
CC(A)
and V
CC(B)
) which enable
bidirectional level translation. Both V
CC(A)
and V
CC(B)
can be supplied at any voltage
between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low
voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to
V
CC(A)
and pin B is referenced to V
CC(B)
. A HIGH on DIR allows transmission from A to B
and a LOW on DIR allows transmission from B to A.
Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall
times across the entire V
CC(A)
and V
CC(B)
ranges. The device ensures low static and
dynamic power consumption and is fully specified for partial power-down applications
using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow
current through the device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at GND, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 1.1 V to 3.6 V
V
CC(B)
: 1.1 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9 A (maximum)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
74AUP1T45
Low-power dual supply translating transceiver; 3-state
Rev. 5 — 9 August 2012 Product data sheet
