74AUP1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 9 August 2012 26 of 36
NXP Semiconductors
74AUP1T45
Low-power dual supply translating transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 10 shows the 74AUP1T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable (OE) pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
Table 12 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
[1] System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.
[2] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.
Fig 10. Bidirectional logic level-shifting application
System-1
I/O-2I/O-1
74AUP1T45
V
CC(A)
V
CC(B)
V
CC2
V
CC1
V
CC1
DIR CTRL
GND
AB
001aae970
1
2
3
6
DIR
5
4
V
CC2
PULL-UP/DOWN
OR
BUSHOLD
System-2
PULL-UP/DOWN
OR
BUSHOLD
Table 12. Description bidirectional logic level-shifting application
[1][2]
State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on the pull-up or pull-down.
3 L Z Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The
bus-line state depends on the pull-up or pull-down.
4 L input output system-2 data to system-1
