NCP5424
http://onsemi.com
3
MAXIMUM RATINGS
Rating Value Unit
Operating Junction Temperature, T
J
150 °C
Storage Temperature Range, T
S
−65 to +150 °C
ESD Susceptibility (Human Body Model) 2.0 kV
Package Thermal Resistance, SOIC−16: Junction−to−Case, R
JC
Junction−to−Ambient, R
JA
28
115
°C/W
°C/W
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Symbol Pin Name V
MAX
V
MIN
I
SOURCE
I
SINK
V
CC
IC Power Input 16 V −0.3 V N/A 1.5 A peak, 200 mA DC
COMP1, COMP2 Compensation Capacitor for Channel 1 or 2 4.0 V −0.3 V 1.0 mA 3.5 mA
V
FB1
, V
FB+2
, V
FB−2
Voltage Feedback Input for Channel 1 or 2 5.0 V −0.3 V 1.0 mA 1.0 mA
BST Power Input for GATE(H)1, 2 20 V −0.3 V N/A 1.5 A peak, 200 mA DC
R
OSC
Oscillator Resistor 4.0 V −0.3 V 1.0 mA 1.0 mA
GATE(H)1
,
GATE(H)2
High−Side FET Driver for Channel 1 or 2 20 V −0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC
GATE(L)1
,
GATE(L)2 Low−Side FET Driver for Channel 1 or 2 16 V −0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC
GND Ground 0 V 0 V 1.5 A peak, 200 mA DC N/A
IS+1, IS+2 Positive Current Sense for Channel 1 or 2 6.0 V −0.3 V 1.0 mA 1.0 mA
IS− Negative Current Sense for Channels 1 and 2 6.0 V −0.3 V 1.0 mA 1.0 mA
PACKAGE PIN DESCRIPTION
PIN # SYMBOL FUNCTION
1 GATE(H)1 High Side Switch FET driver pin for channel 1.
2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1.
3 GND Ground pin for all circuitry contained in the IC. This pin is internally bonded to the substrate of the IC.
4 BST Power input for GATE(H)1 and GATE(H)2 pins.
5 IS+1 Positive input for channel 1 overcurrent comparator.
6 IS− Negative input for channels 1 and 2 overcurrent comparator.
7 V
FB1
Error amplifier inverting input for channel 1.
8 COMP1 Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation.
The same capacitor provides Soft−Start timing for channel 1. This pin also disables the channel 1 output when pulled
below 0.3 V.
9 COMP2 Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation
and Soft−Start timing for channel 2. Channel 2 output is disabled when this pin is pulled below 0.3 V.
10 V
FB−2
Error amplifier inverting input for channel 2.
11 V
FB+2
Error amplifier noninverting input for channel 2.
12 IS+2 Positive input for channel 2 overcurrent comparator.
13 R
OSC
Oscillator frequency pin. A resistor from this pin to ground sets the oscillator frequency.
14 V
CC
Input Power supply pin.
15 GATE(L)2 Low Side Synchronous FET driver pin for channel 2.
16 GATE(H)2 High Side Switch FET driver pin for channel 2.
