NCP5424
http://onsemi.com
16
R
SENSE
0.070 V
I
LIMIT
In a high current supply, the sense resistor will be a very
low value, typically less than 10 m. Such a resistor can be
either a discrete component or a PCB trace. The resistance
value of a discrete component can be more precise than a
PCB trace, but the cost is also greater.
Setting the current limit using an external sense resistor is
very precise because all the values can be designed to
specific tolerances. However, the disadvantage of using a
sense resistor is its additional constant power loss and heat
generation.
Inductor ESR. Another means of sensing current is to use
the intrinsic resistance of the inductor. A model of an
inductor reveals that the windings of an inductor have an
effective series resistance (ESR).
The voltage drop across the inductor ESR can be
measured with a simple parallel circuit: an RC integrator. If
the value of R
S1
and C are chosen such that:
L
ESR
R
S1
C
then the voltage measured across the capacitor C will be:
V
C
ESR I
LIM
Selecting Components.
Select the capacitor C first. A
value of 0.1 F is recommended. The value of R
S1
can be
selected according to:
R
S1
1
ESR C
Typical values for inductor ESR range in the low m;
consult manufacturer’s datasheet for specific details.
Selection of components at these values will result in a
current limit of:
I
LIM
0.070 V
ESR
Figure 9. Inductor ESR Current Sensing
GATE(H)
V
CC
Co
GATE(L)
IS+
IS−
RS1
C
ESR
L
Given an ESR value of 3.5 m, the current limit becomes
20 A. If an increased current limit is required, a resistor
divider can be added.
The advantages of setting the current limit by using the
winding resistance of the inductor are that efficiency is
maximized and heat generation is minimized. The tolerance
of the inductor ESR must be factored into the design of the
current limit. Finally, one or two more components are
required for this approach than with resistor sensing.
Adding External Slope Compensation
Today’s voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (V
FB
),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
internal slope compensation is insufficient, the performance
of the NCP5424−based regulator can be improved through
the addition of a fixed amount of external slope
compensation at the output of the PWM Error Amplifier (the
COMP pin) during the regulator off−time. Referring to
Figure 8, the amount of voltage ramp at the COMP pin is
dependent on the gate voltage of the lower (synchronous)
FET and the value of resistor divider formed by R1and R2.
V
SLOPECOMP
V
GATE(L)
R2
R1 R2
(1 e
−t
)
where:
V
SLOPECOMP
= amount of slope added;
V
GATE(L)
= lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t
ON
or t
OFF
(switch off−time);
τ = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
Figure 10. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
Each On−Time Cycle
To Synchronous
FET
C1
R2
R1
NCP5424
GATE(L)
COMP
C
COMP
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
