Altera Corporation 39
FLEX 6000 Programmable Logic Device Family Data Sheet
Table 20. IOE Timing Microparameters Note (1)
Symbol Parameter Conditions
t
OD1
Output buffer and pad delay, slow slew rate = off, V
CCIO
= V
CCINT
C1 = 35 pF (2)
t
OD2
Output buffer and pad delay, slow slew rate = off, V
CCIO
= low voltage C1 = 35 pF (3)
t
OD3
Output buffer and pad delay, slow slew rate = on C1 = 35 pF (4)
t
XZ
Output buffer disable delay C1 = 5 pF
t
ZX1
Output buffer enable delay, slow slew rate = off, V
CCIO
= V
CCINT
C1 = 35 pF (2)
t
ZX2
Output buffer enable delay, slow slew rate = off, V
CCIO
= low voltage C1 = 35 pF (3)
t
ZX3
IOE output buffer enable delay, slow slew rate = on C1 = 35 pF (4)
t
IOE
Output enable control delay
t
IN
Input pad and buffer to FastTrack Interconnect delay
t
IN_DELAY
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
Table 21. Interconnect Timing Microparameters Note (1)
Symbol Parameter Conditions
t
LOCAL
LAB local interconnect delay
t
ROW
Row interconnect routing delay (5)
t
COL
Column interconnect routing delay (5)
t
DIN_D
Dedicated input to LE data delay (5)
t
DIN_C
Dedicated input to LE control delay
t
LEGLOBAL
LE output to LE control via internally-generated global signal delay (5)
t
LABCARRY
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
t
LABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Table 22. External Reference Timing Parameters
Symbol Parameter Conditions
t
1
Register-to-register test pattern (6)
t
DRR
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
(7)
