LTC3553-2
24
35532f
OPERATION
supply voltages where loss of regulation or other unde-
sirable operation may occur. In applications where the
buck input is supplied from other than the V
OUT
pin, other
measures should be taken to ensure that the buck is not
operated outside the specifi ed BVIN input supply range,
as operation beyond this range is not guaranteed.
LDO Regulator UVLO Considerations
The LDO regulator’s bias current is supplied via an internal
connection to the USB PowerPath V
OUT
pin. The V
OUT
UVLO
shuts down the LDO when V
OUT
drops below about 2.6V
in order to prevent the LDO from operating incorrectly
due to too low a bias supply voltage.
The LDO power input pin, V
INLDO
, can be driven with as
little as 1.65V. There is, however, no UVLO to enforce this
r e q u ir e m e n t . I t i s t h u s r e c o m m e n d e d t h a t V
INLDO
be tied to
the USB PowerPath V
OUT
pin, to ensure proper operation.
PUSHBUTTON INTERFACE
State Diagram/Operation
Figure 5 shows the LTC3553-2 pushbutton state diagram.
The pushbutton state machine has a clock with 1.82ms
period.
Upon fi rst application of power, V
BUS
or BAT, an inter-
nal power on reset (POR) signal places the pushbutton
circuitry into the power-down (PDN1) state. One second
after entering the PDN1 state the pushbutton circuitry will
transition into the hard reset (HR) state.
In the HR state, all supplies are disabled. The PowerPath
circuitry is placed in an ultralow quiescent state to minimize
battery drain. If no external charging supply is present
(V
BUS
) then the ideal diode is shut down, disconnecting
V
OUT
from BAT to further minimize battery drain. The ultra-
low power consumption in the HR state makes it ideal for
shipping or long term storage, minimizing battery drain.
The following events cause the state machine to transition
out of HR into the power-up (PUP1) state:
ON input low for 400ms (PB400MS)
Application of external power (EXTPWR)
Upon entering the PUP1 state, the pushbutton circuitry
will sequence up the LDO and buck regulators. The buck
regulator is enabled once the feedback voltage of the LDO
nears regulation.
The BUCK_ON input is ignored in the PUP1 state. The
state machine remains in the PUP1 state for fi ve seconds.
During the fi ve seconds, the application’s microprocessor,
powered by the regulators, has time to boot and assert
BUCK_ON. Five seconds after entering the PUP1 state,
the pushbutton circuitry automatically transitions into the
power-on (PON) state.
In the PON state, the buck regulator can be enabled and
shut down at any time by the BUCK_ON pin. A high on
BUCK_ON is needed to keep the buck enabled. To remain
in the PON state, the application circuit must keep the
BUCK_ON input high, else the state machine enters the
power-down (PDN2) state.
When BUCK_ON is low, or when V
OUT
drops to its under-
voltage lockout (V
OUT
UVLO) threshold, the state machine
will leave the PON state and enter the power-down (PDN2)
state. In the power-down state (PDN2), the buck regulator
is kept disabled regardless of the state of the BUCK_ON
pin. The state machine remains in the power-down state
for one second, before automatically entering the power-
off (POFF) state. This one second delay allows the buck
Figure 5. Pushbutton State Diagram
35532 F07
PUP2
PDN1
PDN2
HRST
HRST
HRST
POR
UVLO AND
BUCK_ON
BUCK_ON
EXTPWR OR
PB400MS
1SEC
5SEC
5SEC
1SEC
PON
PUP1
HR
UVLO OR
BUCK_ON
EXTPWR OR
PB400MS
POFF
