LTC3553-2
25
35532f
output time to power down completely before it can be
re-enabled.
The same events used to exit the hard reset (HR) state
are also used to exit the POFF state and enter the PUP2
state. The PUP2 state operates in a similar manner as the
PUP1 state previously described.
Both regulators remain powered up during the fi ve second
power-up (PUP1 or PUP2) period, regardless of the state
of the BUCK_ON input.
In either the HR or POFF states, if the BUCK_ON pin is
driven high, the pushbutton circuitry directly enters the
PON state, without passing through the power-up (PUP1
or PUP2) states.
Starting from the HR state, bringing the BUCK_ON pin high
enables the PowerPath, if it wasn’t already enabled due
to V
BUS
power being available. This powers up the V
OUT
pin from V
BUS
or BAT. When the V
OUT
voltage rises above
the V
OUT
UVLO threshold, the state machine transitions
from the HR state into the PON state. At this point both
the LDO and buck regulator will simultaneously turn on.
The hard reset (HRST) event is generated by pressing and
holding the pushbutton (ON input low) for 14 seconds. For
a valid HRST event to occur the button press must start in
the PUP1, PUP2 or PON state, but can end in any state. If
a valid HRST event is present in PON, PDN2 or POFF, then
the state machine will transition to the PDN1 state and
subsequently transition to the HR state one second later.
Debounced Pushbutton Output (PBSTAT)
In the PON, PUP1, and PUP2 states, the PBSTAT open-
drain output pin outputs a debounced version of the ON
pushbutton signal. ON must be held low for at least 50ms
for the pushbutton interface to recognize it and cause
PBSTAT to go low. PBSTAT goes high impedance when
ON goes high, except the logic enforces a minimum pulse
width of 50ms on PBSTAT.
In the HR, POFF, PDN1, and PDN2 states, PBSTAT remains
high impedance regardless of the state of ON.
Power-Up Via Pushbutton Press from Hard Reset
Figure 6 shows the LTC3553-2 powering up through ap-
plication of the external pushbutton. For this example the
pushbutton circuitry starts in the HR state with a battery
connected. Pushbutton application (ON low) for 400ms
transitions the pushbutton circuitry into the PUP1 state
and powers up the LDO followed by the buck. If BUCK_ON
goes low after the fi ve second period the buck regulator
will be shut down.
PGOOD is asserted once all enabled regulators are within
8% of their regulation voltage for 1.8ms. The BUCK_ON
input can be driven via a P/C or by one of the regulator
outputs through a high impedance (100kΩ typical) to keep
the buck enabled as described above. PBSTAT does not
go low on initial pushbutton application for power-up, but
will go low with subsequent ON pushbutton applications
in the PUP1, PUP2 or PON states.
OPERATION
Figure 6. Power-Up via Pushbutton Press
BAT
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
BUS
ON (PB)
PBSTAT
LDO
BUCK
PGOOD
BUCK_ON
STATE HR PONPUP1
35532 F06
1.8ms
400ms
LTC3553-2
26
35532f
Power-Up Via Applying External Power from Power Off
Figure 7 shows the LTC3553-2 powering up through ap-
plication of external power (V
BUS
). For this example the
pushbutton circuitry starts in the POFF state with a battery
connected. 100ms after V
BUS
application the pushbutton
circuitry transitions into the PUP2 state and powers up the
buck. The 100ms delay time allows the applied supply to
settle. The buck regulator will stay powered as long as the
BUCK_ON input is driven high before the fi ve second PUP2
period is over. If the BUCK_ON is low or goes low after the
ve second period the buck regulator will be shut down. In
the above example the BUCK_ON pin is high at the end of the
ve second period and therefore the buck regulator con-
tinues to stay on at the end of the fi ve second period. In
this example, PGOOD is initially high as the always-on
LDO is enabled. At the end of 100ms, the input power at
V
BUS
is validated and the buck regulator is enabled at this
OPERATION
point PGOOD goes low and will stay low until the buck
regulator is within 8% of its regulation voltage for 1.8ms.
The BUCK_ON input can be driven via a P/C or one of
the regulator outputs through a high impedance (100k
typ) to keep the buck regulator enabled as described above.
Without a battery present, initial power application causes
a power-on reset which puts the pushbutton circuitry in
the PDN1 state and subsequently the HR state one second
later. At this time, if a valid supply voltage is detected at
the BUS pin (i.e., V
BUS
> V
UVLO
and V
BUS
– V
BAT
> V
DUVLO
),
the pushbutton circuity immediately enters the PUP1 state.
For this to work reliably, the BAT pin voltage must be kept
well-behaved when no battery is connected. Ensure this
by bypassing the BAT pin to GND with an RC network con-
sisting of a 100µF ceramic capacitor in series with 0.3.
Figure 7. Power-Up via Applying External Power
BAT
V
BUS
ON (PB)
PBSTAT
BUCK
LDO
PGOOD
BUCK_ON
STATE POFF PONPUP2
35532 F07
5s
1.8ms
100ms
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
LTC3553-2
27
35532f
OPERATION
Power-Up Via Asserting the BUCK_ON Pin
Figure 8 shows the LTC3553-2 powering up by driving
BUCK_ON high. For this example the pushbutton circuitry
starts in the HR state with a battery connected. Once
BUCK_ON goes high, the pushbutton circuitry enters the
PON state and the buck powers up. Also, as the part exits
the hard reset state the LDO will power up simultaneously.
The PGOOD is initially low and will go high once both regu-
lators are within 8% of their regulation voltage for 1.8ms.
Powering up via asserting the BUCK_ON pin is useful
for applications containing an always-on C that’s not
powered by the LTC3553-2 regulators. That C can power
the application up and down for housekeeping and other
activities not needing the user’s control.
Power-Down by De-Asserting BUCK_ON
Figure 9 shows the LTC3553-2 powering down by C/
P control. For this example the pushbutton circuitry
starts in the PON state with a battery connected and both
regulators enabled. The user presses the pushbutton (ON
low) for at least 50ms, which generates a debounced, low
impedance pulse on the PBSTAT output. After receiving
the PBSTAT signal, the C/P software decides to drive
the BUCK_ON input low in order to power down. After
the BUCK_ON input goes low, the pushbutton circuitry
will enter the PDN2 state. In the PDN2 state a one second
wait time is initiated after which the pushbutton circuitry
enters the POFF state. During this one second time, the
ON, and BUCK_ON inputs as well as external power ap-
plication are ignored. Though the above assumes a battery
Figure 8. Power-Up via Asserting the BUCK_ON Pin
Figure 9. Power-Down via De-Assertion of BUCK_ON
BAT
V
BUS
ON (PB)
PBSTAT
BUCK
LDO
BUCK_ON
STATE HR PON
35532 F08
1
0
1
0
1
0
1
0
1
0
1
0
1
0
PGOOD
1
0
1.8ms
BAT
V
BUS
ON (PB)
PBSTAT
BUCK
LDO
PGOOD
BUCK_ON
STATE PON POFFPDN2
35532 F09
1s
μC/μP CONTROL
50ms
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

LTC3553EUD-2#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Micropower USB Power Manager with Li-Ion Charger, LDO, and Buck Regulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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