Sensors
22 NXP Semiconductors
MMA8452Q
0x0B: SYSMOD system mode register
The system mode register indicates the current device operating mode. Applications using the auto-sleep/wake mechanism
should use this register to synchronize the application with the device operating mode transitions.
0x0C: INT_SOURCE system interrupt status register
In the interrupt source register the status of the various embedded features can be determined. The bits that are set (logic ‘1’)
indicate which function has asserted an interrupt and conversely the bits that are cleared (logic ‘0’) indicate which function has
not asserted or has deasserted an interrupt. The bits are set by a low to high transition and are cleared by reading the
appropriate interrupt source register. The SRC_DRDY bit is cleared by reading the X, Y and Z data. It is not cleared by simply
reading the status register (0x00).
0x0B: SYSMOD: system mode register (read only)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
0 0 0 0 0 0 SYSMOD1 SYSMOD0
Table 13. SYSMOD description
Field Description
SYSMOD[1:0]
System mode. Default value: 00.
00: Standby mode
01: Wake mode
10: Sleep mode
0x0C: INT_SOURCE: system interrupt status register (read only)
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SRC_ASLP 0 SRC_TRANS SRC_LNDPRT SRC_PULSE SRC_FF_MT 0 SRC_DRDY
Table 14.
INT_SOURCE description
Field Description
SRC_ASLP
Auto-sleep/wake interrupt status bit. Default value: 0.
Logic ‘1’ indicates that an interrupt event that can cause a wake to sleep or sleep to wake system mode transition has
occurred.
Logic ‘0’ indicates that no wake to sleep or sleep to wake system mode transition interrupt event has occurred.
wake to sleep transition occurs when no interrupt occurs for a time period that exceeds the user specified limit
(ASLP_COUNT). This causes the system to transition to a user specified low ODR setting.
sleep to wake transition occurs when the user specified interrupt event has woken the system; thus causing the system
to transition to a user specified high ODR setting.
Reading the SYSMOD register clears the SRC_ASLP bit.
SRC_TRANS
Transient interrupt status bit. Default value: 0.
Logic ‘1’ indicates that an acceleration transient value greater than user specified
threshold
has
occurred. Logic ‘0’
indicates that no transient event has occurred.
This bit is asserted whenever
EA bit in the TRANS_SRC is asserted and
the
interrupt
has been enabled. This bit is
cleared by reading the TRANS_SRC register.
SRC_LNDPRT
Landscape/portrait orientation interrupt status bit. Default value: 0.
Logic ‘1’ indicates that an interrupt was generated due to a change in the device orientation status. Logic ‘0’ indicates
that no change in orientation status was detected.
This bit is asserted whenever NEWLP bit in the PL_STATUS is asserted and the
interrupt
has
been enabled.
This bit is cleared by reading the PL_STATUS register.
SRC_PULSE
Pulse interrupt status bit. Default value: 0.
Logic ‘1’ indicates that an interrupt was generated due to single and/or double pulse event. Logic ‘0’ indicates that no
pulse event was detected.
This bit is asserted whenever EA bit in the PULSE_SRC is asserted and the interrupt has been enabled.
This bit is cleared by reading the PULSE_SRC register.
