101990016

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54

Sensors

NXP Semiconductors 43

MMA8452Q

The corresponding functional block interrupt enable bit allows the functional block to route its event detection flags to the system’s

interrupt controller. The interrupt controller routes the enabled functional block interrupt to the INT1 or INT2 pin.

0x2E: CTRL_REG5 register (read/write)

The system’s interrupt controller shown in Figure 10 uses the corresponding bit field in the CTRL_REG5 register to determine the

routing table for the INT1 and INT2 interrupt pins. If the bit value is logic ‘0’, the functional block’s interrupt is routed to INT2, and

if the bit value is logic ‘1’, then the interrupt is routed to INT1. One or more functions can assert an interrupt pin; therefore a host

application responding to an interrupt should read the INT_SOURCE (0x0C) register to determine the appropriate sources of the

interrupt.

6.8 User offset correction registers

For more information on how to calibrate the 0 g offset, refer to application note AN4069. The 2’s complement offset correction

registers values are used to realign the zero-g position of the X, Y, and Z-axis after device board mount. The resolution of the

offset registers is 2 mg per LSB. The 2’s complement 8-bit value would result in an offset compensation range ±256 mg.

0x2F: OFF_X offset correction X register

INT_EN_LNDPRT

Interrupt enable. Default value: 0.

0: Orientation (landscape/portrait) interrupt disabled.

1: Orientation (landscape/portrait) interrupt enabled.

INT_EN_PULSE

Interrupt enable. Default value: 0.

0: Pulse detection interrupt disabled; 1: Pulse detection interrupt enabled

INT_EN_FF_MT

Interrupt enable. Default value: 0.

0: Freefall/motion interrupt disabled; 1: Freefall/motion interrupt enabled

INT_EN_DRDY

Interrupt enable. Default value: 0.

0: Data-ready interrupt disabled; 1: Data-ready interrupt enabled

0x2E: CTRL_REG5 interrupt configuration register

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

INT_CFG_ASLP 0 INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT 0 INT_CFG_DRDY

Table 62.

Interrupt configuration register description

Field Description

INT_CFG_ASLP

INT1/INT2 configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_TRANS

INT1/INT2 configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_LNDPRT

INT1/INT2 configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_PULSE

INT1/INT2 configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_FF_MT

INT1/INT2 configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_DRDY

INT1/INT2 configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

0x2F: OFF_X register (read/write)

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

D7 D6 D5 D4 D3 D2 D1 D0

Table 61. Interrupt enable register description (continued)

Field Description

Sensors

44 NXP Semiconductors

MMA8452Q

0x30: OFF_Y offset correction Y register

0x31: OFF_Z offset correction Z register

Table 63. OFF_X description

Field Description

D[7:0]

X-axis offset value. Default value: 0000_0000.

0x30: OFF_Y register (read/write)

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

D7 D6 D5 D4 D3 D2 D1 D0

Table 64. OFF_Y description

Field Description

D[7:0]

Y-axis offset value. Default value: 0000_0000.

0x31: OFF_Z register (read/write)

Bit

7

Bit

6

Bit

5

Bit

4

Bit

3

Bit

2

Bit

1

Bit

0

D7 D6 D5 D4 D3 D2 D1 D0

Table 65. OFF_Z description

Field Description

D[7:0]

Z-axis offset value. Default value: 0000_0000.

Table 66. MMA8452Q register map

Reg Name Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 STATUS Data Status R ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

01 OUT_X_MSB 12-bit X data R XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4

02 OUT_X_LSB 12-bit X data R XD3 XD2 XD1 XD0 0 0 0 0

03 OUT_Y_MSB 12-bit Y data R YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4

04 OUT_Y_LSB 12-bit Y data R YD3 YD2 YD1 YD0 0 0 0 0

05 OUT_Z_MSB 12-bit Z data R ZD11 ZD10 ZD9 ZD8 ZD7 ZD6 ZD5 ZD4

06 OUT_Z_LSB 12-bit Z data R ZD3 ZD2 ZD1 ZD0 0 0 0 0

0B SYSMOD System mode R 0 0 0 0 0 0 SYSMOD1 SYSMOD0

0C INT_SOURCE Interrupt Status R SRC_ASLP 0 SRC_TRANS SRC_LNDPRT SRC_PULSE SRC_FF_MT 0 SRC_DRDY

0D WHO_AM_I ID Register R 0 0 1 0 1 0 1 0

0E XYZ_DATA_CFG Data Config R/W 0 0 0 HPF_OUT 0 0 FS1 FS0

0F HP_FILTER_CUTOFF HP Filter Setting R/W 0 0 Pulse_HPF_BYP Pulse_LPF_EN 0 0 SEL1 SEL0

10 PL_STATUS PL Status R NEWLP LO 0 0 0 LAPO[1] LAPO[0] BAFRO

11 PL_CFG PL Configuration R/W DBCNTM PL_EN 0 0 0 0 0 0

12 PL_COUNT PL DEBOUNCE R/W DBNCE[7] DBNCE[6] DBNCE[5] DBNCE[4] DBNCE[3] DBNCE[2] DBNCE[1] DBNCE[0]

13 PL_BF_ZCOMP

PL Back/Front Z Comp

R

BKFR[1] BKFR[0] 0 0 0 ZLOCK[2] ZLOCK[1] ZLOCK[0]

14 PL_THS_REG PL THRESHOLD R PL_THS[4] PL_THS[3] PL_THS[2] PL_THS[1] PL_THS[0] HYS[2] HYS[1] HYS[0]

15 FF_MT_CFG

Freefall/Motion Config

R/W

ELE OAE ZEFE YEFE XEFE 0 0 0

16 FF_MT_SRC

Freefall/Motion Source

R

EA 0 ZHE ZHP YHE YHP XHE XHP

17 FF_MT_THS

Freefall/Motion threshold

R/W

DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0

Sensors

NXP Semiconductors 45

MMA8452Q

18 FF_MT_COUNT

Freefall/Motion

Debounce R/W

D7 D6 D5 D4 D3 D2 D1 D0

1D TRANSIENT_CFG Transient Config R/W 0 0 0 ELE ZTEFE YTEFE XTEFE HPF_BYP

1E TRANSIENT_SRC Transient Source R 0 EA ZTRANSE Z_Trans_Pol YTRANSE Y_Trans_Pol XTRANSE X_Trans_Pol

1F TRANSIENT_THS Transient threshold R/W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0

20 TRANSIENT_COUNT

Transient Debounce

R/W

D7 D6 D5 D4 D3 D2 D1 D0

21 PULSE_CFG Pulse Config R/W DPA ELE ZDPEFE ZSPEFE YDPEFE YSPEFE XDPEFE XSPEFE

22 PULSE_SRC Pulse Source R EA AxZ AxY AxX DPE Pol_Z Pol_Y Pol_X

23 PULSE_THSX Pulse X Threshold R/W 0 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0

24 PULSE_THSY Pulse Y Threshold R/W 0 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0

25 PULSE_THSZ Pulse Z Threshold R/W 0 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0

26 PULSE_TMLT Pulse First Timer R/W TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0

27 PULSE_LTCY Pulse Latency R/W LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0

28 PULSE_WIND

Pulse 2nd Window

R/W

WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0

29 ASLP_COUNT

Auto-sleep Counter

R/W

D7 D6 D5 D4 D3 D2 D1 D0

2A CTRL_REG1 Control Reg1 R/W ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTIVE

2B CTRL_REG2 Control Reg2 R/W ST RST 0 SMODS1 SMODS0 SLPE MODS1 MODS0

2C CTRL_REG3

Control Reg3

(wake Interrupts from

sleep) R/W

0 WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT 0 IPOL PP_OD

2D CTRL_REG4

Control Reg4

(Interrupt Enable Map)

R/W

INT_EN_ASLP 0 INT_EN_TRANS INT_EN_LNDPRT INT_EN_PULSE INT_EN_FF_MT 0 INT_EN_DRDY

2E CTRL_REG5

Control Reg5

(Interrupt Configuration)

R/W

INT_CFG_ASLP 0 INT_CFG_TRANS

INT_CFG_LNDPR

T

INT_CFG_PULSE INT_CFG_FF_MT 0 INT_CFG_DRDY

2F OFF_X X 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0

30 OFF_Y Y 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0

31 OFF_Z Z 8-bit offset R/W D7 D6 D5 D4 D3 D2 D1 D0

Table 67. Accelerometer output data

12-bit data Range ±2 g (1 mg) Range ±4 g (2 mg) Range ±8 g (3.9 mg)

0111 1111 1111 1.999 g +3.998 g +7.996 g

0111 1111 1110 1.998 g +3.996 g +7.992 g

…… … …

0000 0000 0001 0.001 g +0.002 g +0.004 g

0000 0000 0000 0.0000 g 0.0000 g 0.0000 g

1111 1111 1111 –0.001 g –0.002 g –0.004 g

…… … …

1000 0000 0001 –1.999 g –3.998 g –7.996 g

1000 0000 0000 –2.0000 g –4.0000 g –8.0000 g

8-bit data Range ±2 g (15.6 mg) Range ±4 g (31.25 mg) Range ±8 g (62.5 mg)

0111 1111 1.9844 g +3.9688 g +7.9375 g

0111 1110 1.9688 g +3.9375 g +7.8750 g

…… … …

Table 66. MMA8452Q register map (continued)

Reg Name Definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54

101990016

Mfr. #:

Manufacturer:

Seeed Studio

Description:

Acceleration Sensor Development Tools TESSEL ACCELEROMETER MODULE

Lifecycle:

New from this manufacturer.

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