101990016 Datasheet 101990016 | P37-P39

Sensors

NXP Semiconductors 37

MMA8452Q

0x27: PULSE_LTCY pulse latency timer register

The bits LTCY7 through LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses

are ignored. Note: This timer must be set for single pulse and for double pulse.

The minimum time step for the pulse latency is defined in Table 45 and Table 46. The maximum time is the time step at the ODR

and oversampling mode multiplied by 255. The timing also changes when the pulse LPF is enabled or disabled.

0x27: PULSE_LTCY register (read/write)

Bit

LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0

Table 44. PULSE_LTCY description

Field Description

LTCY[7:0]

Latency time limit. Default value: 0000_0000

Table 45. Time step for pulse latency @ ODR and power mode (register 0x0F) Pulse_LPF_EN = 1

ODR (Hz)

Max time range (s) Time step (ms)

Normal LPLN HighRes LP Normal LPLN HighRes LP

800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5

4001.2761.2761.2761.2765555

200 2.56 2.56 1.276 2.56 10 10 5 10

100 5.1 5.1 1.276 5.1 20 20 5 20

50 10.2 10.2 1.276 10.2 40 40 5 40

12.5 10.2 40.8 1.276 40.8 40 160 5 160

6.25 10.2 40.8 1.276 81.6 40 160 5 320

1.56 10.2 40.8 1.276 81.6 40 160 5 320

Table 46. Time step for pulse latency @ ODR and power mode (register 0x0F) Pulse_LPF_EN = 0

ODR (Hz)

Max time range (s) Time step (ms)

Normal LPLN HighRes LP Normal LPLN HighRes LP

800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25

400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5

200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5

100 1.276 1.276 0.318 2.56 5 5 1.25 10

50 2.56 2.56 0.318 5.1 10 10 1.25 20

12.5 2.56 10.2 0.318 20.4 10 40 1.25 80

6.25 2.56 10.2 0.318 20.4 10 40 1.25 80

1.56 2.56 10.2 0.318 20.4 10 40 1.25 80

Sensors

38 NXP Semiconductors

MMA8452Q

0x28: PULSE_WIND register (read/write)

The bits WIND7 through WIND0 define the maximum interval of time that can elapse after the end of the latency interval in which

the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The

detected second pulse width must be shorter than the time limit constraints specified by the PULSE_TMLT register, but the end

of the double pulse need not finish within the time specified by the PULSE_WIND register.

The minimum time step for the pulse window is defined in Ta ble 48 and Table 49. The maximum time is the time step at the ODR,

oversampling mode and LPF filter option multiplied by 255.

0x28: PULSE_WIND second pulse time window register

Bit

WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0

Table 47. PULSE_WIND description

Field Description

WIND[7:0]

Second pulse time window. Default value: 0000_0000.

Table 48. Time step for PULSE detection window @ ODR and power mode (register 0x0F) Pulse_LPF_EN = 1

ODR (Hz)

Max time range (s) Time step (ms)

Normal LPLN HighRes LP Normal LPLN HighRes LP

800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5

400 1.276 1.276 1.276 1.276 5 5 5 5

200 2.56 2.56 1.276 2.56 10 10 5 10

100 5.1 5.1 1.276 5.1 20 20 5 20

50 10.2 10.2 1.276 10.2 40 40 5 40

12.5 10.2 40.8 1.276 40.8 40 160 5 160

6.25 10.2 40.8 1.276 81.6 40 160 5 320

1.56 10.2 40.8 1.276 81.6 40 160 5 320

Table 49. Time step for PULSE detection window @ ODR and power mode (register 0x0F) Pulse_LPF_EN = 0

ODR (Hz)

Max time range (s) Time step (ms)

Normal LPLN HighRes LP Normal LPLN HighRes LP

800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25

400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5

200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5

100 1.276 1.276 0.318 2.56 5 5 1.25 10

50 2.56 2.56 0.318 5.1 10 10 1.25 20

12.5 2.56 10.2 0.318 20.4 10 40 1.25 80

6.25 2.56 10.2 0.318 20.4 10 40 1.25 80

1.56 2.56 10.2 0.318 20.4 10 40 1.25 80

Sensors

NXP Semiconductors 39

MMA8452Q

6.6 Auto-wake/sleep detection

The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value

specified in the DR[2:0] register to ASLP_RATE register value, provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2

register. See Table 52 for functional blocks that may be monitored for inactivity in order to trigger the return to sleep event.

D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum value

depend on the ODR chosen as shown in Table 51.

In order to wake the device, the desired function or functions must be enabled in CTRL_REG4 and set to wake to sleep in

CTRL_REG3. All enabled functions will still function in sleep mode at the sleep ODR. Only the functions that have been selected

for wake from sleep will wake the device.

MMA8452Q has four functions that can be used to keep the sensor from falling asleep; transient, orientation, pulse, and motion/

FF. One or more of these functions can be enabled. In order to wake the device, four functions are provided; transient, orientation,

pulse, and the motion/freefall. The auto-wake/sleep interrupt does not affect the wake/sleep, nor does the data-ready interrupt.

See register 0x2C for the wake from sleep bits.

If the auto-sleep bit is disabled, then the device can only toggle between standby and wake mode. If auto-sleep interrupt is

enabled, transitioning from active mode to auto-sleep mode and vice versa generates an interrupt.

0x29: ASLP_COUNT Register (read/write)

Bit

D7 D6 D5 D4 D3 D2 D1 D0

Table 50. ASLP_COUNT description

Field Description

D[7:0]

Duration value. Default value: 0000_0000.

Table 51. ASLP_COUNT r with ODR

Output data rate (ODR) Duration ODR time step ASLP_COUNT step

800 Hz 0 to 81 s 1.25 ms 320 ms

400 Hz 0 to 81 s 2.5 ms 320 ms

200 Hz 0 to 81 s 5 ms 320 ms

100 Hz 0 to 81 s 10 ms 320 ms

50 Hz 0 to 81 s 20 ms 320 ms

12.5 Hz 0 to 81 s 80 ms 320 ms

6.25 Hz 0 to 81 s 160 ms 320 ms

1.56 Hz 0 to 162 s 640 ms 640 ms

Table 52. Sleep/wake mode gates and triggers

Interrupt source

Event restarts timer and

delays return to sleep

Event will wake from sleep

SRC_TRANS Yes Yes

SRC_LNDPRT Yes Yes

SRC_PULSE Yes Yes

SRC_FF_MT Yes Yes

SRC_ASLP No* No*

SRC_DRDY No No

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101990016

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Acceleration Sensor Development Tools TESSEL ACCELEROMETER MODULE

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