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CY62136EV30LL-45BVXI
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
CY62136EV30 MoBL
®
Document Number: 38-05569 Rev
. *I
Page 10 of 18
Figure 9. Write Cycle No. 3: WE
Controlled, OE
LOW
[28, 29]
Figure 10. Write Cycle No. 4: BHE
/BLE
Controlled
, OE
LOW
[28]
Switching W
aveforms
(continued)
DATA
IN
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA
I/O
NOTE 30
t
BW
BHE
/BLE
DATA I/O
ADDRESS
t
SD
t
SA
t
HA
t
AW
t
WC
CE
WE
DATA
IN
NOTE 30
t
BW
BHE
/BLE
t
SCE
t
PWE
t
HZWE
t
HD
t
LZWE
Notes
28.
If C
E
goes HIGH simultane
ously with WE
= V
IH
, the output remains in a high impedance st
ate.
29.
The minimum write cycle pulse wid
th should be equal to the sum of t
HZWE
and t
SD
.
30.
During this period,
the I/Os are in output sta
te and input signals should
not be applied.
CY62136EV30 MoBL
®
Document Number: 38-05569 Rev
. *I
Page 1
1 of 18
T
ruth T
able
CE
WE
OE
BHE
BLE
Input
s/Output
s
Mode
Power
H
[31]
XX
X
[31]
X
[31]
High Z
Deselect/power-down
S
tandby (I
SB
)
L
X
X
H
H
High Z
Output disabled
Active (I
CC
)
L
H
L
L
L
Dat
a out (I/O
0
–I/O
15
)
Read
Active (I
CC
)
LHLHL
D
a
t
a
o
u
t
(
I
/
O
0
–I/O
7
);
I/O
8
–I/O
15
in High Z
Read
Active (I
CC
)
L
H
L
L
H
Data Out (I/O
8
–I/O
15
);
I/O
0
–I/O
7
in High Z
Read
Active (I
CC
)
L
H
H
L
L
High Z
Output disabled
Active (I
CC
)
L
H
H
H
L
High Z
O
utput disabled
Active (I
CC
)
L
H
H
L
H
High Z
Output disabled
Active (I
CC
)
L
L
X
L
L
D
ata in (I/O
0
–I/O
15
)
Write
Active (I
CC
)
L
L
X
H
L
Data in (I/O
0
–I/O
7
);
I/O
8
–I/O
15
in High Z
Write
Active (I
CC
)
L
L
X
L
H
Data in (I/O
8
–I/O
15
);
I/O
0
–I/O
7
in High Z
Write
Active (I
CC
)
Note
31.
Chip enable (CE
) and Byte enables (BHE
and BLE
) must be
at fixed CMOS levels (not float
ing). Inte
rmediate voltage level
s
on these pins is not permitted.
CY62136EV30 MoBL
®
Document Number: 38-05569 Rev
. *I
Page 12 of 18
Ordering Code Definitions
Ordering Information
Spe
e
d
(ns)
Ordering
Code
Package
Diagram
Package T
ype
Operating
Range
45
CY62136EV30LL-45BVXI
51-85150
48-ball VFBGA (Pb-free)
Industrial
CY62136EV30LL-45ZSXI
5
1-85087
44-pin TSOP II (Pb-free)
Contact your local Cypr
ess
sales repres
ent
ative for availability of
other part
s
T
emperature Grade: I = Industrial
Pb-free
Package T
ype: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
S
peed Grade: 45 ns
Low Power
V
oltage Range: 3 V typical
Process T
echnology: 9
0 nm
Bus width = × 16
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY
-X
X
621
3
6
E
LL
I
45
X
V30
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
CY62136EV30LL-45BVXI
Mfr. #:
Buy CY62136EV30LL-45BVXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 2Mb 3V 45ns 128K x 16 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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