Document Number: 38-05569 Rev. *I Page 7 of 18
Switching Characteristics
Over the Operating Range
Parameter
[15, 16]
Description
45 ns
Unit
Min Max
Read Cycle
t
RC
Read cycle time 45 – ns
t
AA
Address to data valid – 45 ns
t
OHA
Data hold from address change 10 – ns
t
ACE
CE LOW to data valid – 45 ns
t
DOE
OE LOW to data valid – 22 ns
t
LZOE
OE LOW to Low Z
[17]
5 – ns
t
HZOE
OE HIGH to High Z
[17, 18]
– 18 ns
t
LZCE
CE LOW to Low Z
[17]
10 – ns
t
HZCE
CE HIGH to High Z
[17, 18]
– 18 ns
t
PU
CE LOW to power-up 0 – ns
t
PD
CE HIGH to power-down – 45 ns
t
DBE
BLE/BHE LOW to data valid – 22 ns
t
LZBE
BLE/BHE LOW to Low Z
[17]
5 – ns
t
HZBE
BLE/BHE HIGH to High Z
[17, 18]
– 18 ns
Write Cycle
[19, 20]
t
WC
Write cycle time 45 – ns
t
SCE
CE LOW to write end 35 – ns
t
AW
Address setup to write end 35 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 35 – ns
t
BW
BLE/BHE LOW to write end 35 – ns
t
SD
Data setup to write end 25 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
WE LOW to High Z
[17, 18]
– 18 ns
t
LZWE
WE HIGH to Low Z
[17]
10 – ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in Figure 3 on page 5.
16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
17. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
18. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedence state.
19. The internal write time of the memory is defined by the overlap of WE
, CE
= V
IL
, BHE and BLE = V
IL
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
20. The minimum write pulse for Write Cycle No. 3 (WE
Controlled and OE LOW) should be sum of t
HZWE
and t
SD
.
