M95040, M95020, M95010 DC and AC parameters
31/42
Table 19. AC characteristics (M950x0-W, Device Grade 3)
Test conditions specified in Tabl e 1 1 and Tab l e 9
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCK
Clock frequency D.C. 5 MHz
t
SLCH
t
CSS1
S active setup time 90 ns
t
SHCH
t
CSS2
S not active setup time 90 ns
t
SHSL
t
CS
S deselect time 100 ns
t
CHSH
t
CSH
S active hold time 90 ns
t
CHSL
S not active hold time 90 ns
t
CH
(1)
1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max)
t
CLH
Clock high time 90 ns
t
CL
(1)
t
CLL
Clock low time 90 ns
t
CLCH
(2)
2. Value guaranteed by characterization, not 100% tested in production.
t
RC
Clock rise time 1 µs
t
CHCL
(2)
t
FC
Clock fall time 1 µs
t
DVCH
t
DSU
Data in setup time 20 ns
t
CHDX
t
DH
Data in hold time 30 ns
t
HHCH
Clock low hold time after HOLD not active 70 ns
t
HLCH
Clock low hold time after HOLD active 40 ns
t
CLHL
Clock low setup time before HOLD active 0 ns
t
CLHH
Clock low setup time before HOLD not active 0 ns
t
SHQZ
(2)
t
DIS
Output disable time 100 ns
t
CLQV
t
V
Clock low to output valid 60 ns
t
CLQX
t
HO
Output hold time 0 ns
t
QLQH
(2)
t
RO
Output rise time 50 ns
t
QHQL
(2)
t
FO
Output fall time 50 ns
t
HHQV
t
LZ
HOLD high to output valid 50 ns
t
HLQZ
(2)
t
HZ
HOLD low to output high-Z 100 ns
t
W
t
WC
Write time 5 ms
DC and AC parameters M95040, M95020, M95010
32/42
Table 20. AC characteristics (M950x0-R, device grade 6)
Test conditions specified in Table 11 and Table 10
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCK
Clock frequency D.C. 5 MHz
t
SLCH
t
CSS1
S active setup time 90 ns
t
SHCH
t
CSS2
S not active setup time 90 ns
t
SHSL
t
CS
S deselect time 100 ns
t
CHSH
t
CSH
S active hold time 90 ns
t
CHSL
S not active hold time 90 ns
t
CH
(1)
1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max)
t
CLH
Clock high time 90 ns
t
CL
(1)
t
CLL
Clock low time 90 ns
t
CLCH
(2)
2. Value guaranteed by characterization, not 100% tested in production.
t
RC
Clock rise time 1 µs
t
CHCL
(2)
t
FC
Clock fall time 1 µs
t
DVCH
t
DSU
Data in setup time 20 ns
t
CHDX
t
DH
Data in hold time 30 ns
t
HHCH
Clock low hold time after HOLD not active 70 ns
t
HLCH
Clock low hold time after HOLD active 40 ns
t
CLHL
Clock low setup time before HOLD active 0 ns
t
CLHH
Clock low setup time before HOLD not active 0 ns
t
SHQZ
(2)
t
DIS
Output disable time 100 ns
t
CLQV
t
V
Clock low to output valid 60 ns
t
CLQX
t
HO
Output hold time 0 ns
t
QLQH
(2)
t
RO
Output rise time 50 ns
t
QHQL
(2)
t
FO
Output fall time 50 ns
t
HHQV
t
LZ
HOLD high to output valid 50 ns
t
HLQZ
(2)
t
HZ
HOLD low to output high-Z 100 ns
t
W
t
WC
Write time 5 ms
M95040, M95020, M95010 DC and AC parameters
33/42
Figure 15. Serial input timing
Figure 16. Hold timing
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
Q
AI01448B
S
D
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ

M95020-MN6

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EEPROM 5.5V 2K (256x8)
Lifecycle:
New from this manufacturer.
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