LTC3829
34
3829fc
For more information www.linear.com/LTC3829
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 17. Check the following in the
PC layout:
1. Keep the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under the
IC. The INTV
CC
decoupling capacitor should be placed
immediately adjacent to the IC between the INTV
CC
pin
and PGND plane. A 1µF ceramic capacitor of the X7R or
X5R type is small enough to fit very close to the IC to
minimize the ill effects of the large current pulses drawn
to drive the bottom MOSFETs. An additional 5µF to 10µF
of ceramic, tantalum or other very low ESR capacitance
is recommended in order to keep the internal IC supply
quiet. The power ground returns to the sources of the
bottom N-channel MOSFETs, anodes of the Schottky
diodes and (–) plates of C
IN
, which should have as short
lead lengths as possible.
2. Does the IC DIFFP pin connect to the (+) plates of
C
OUT
? A 30pF to 300pF feedforward capacitor between
the DIFFP and V
FB
pins should be placed as close as
possible to the IC.
3. Are the SENSE
–
and SENSE
+
printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE
+
and
SENSE
–
for each channel should be as close as possible
to the pins of the IC. Connect the SENSE
–
and SENSE
+
pins to the pads of the sense resistor as illustrated in
Figure 1.
4. Do the (+) plates of C
PWR
connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5. Keep the switching nodes, SWn, BOOSTn and TGn away
from sensitive small-signal nodes (SENSE
+
, SENSE
–
,
DIFFP, DIFFN, V
FB
). Ideally the SWn, BOOSTn and
TGn printed circuit traces should be routed away and
separated from the IC and especially the quiet side of
the IC. Separate the high dv/dt traces from sensitive
small-signal nodes with ground traces or ground planes.
6. Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
7. The 47pF to 330pF ceramic capacitor between the I
TH
pin and signal ground should be placed as close as pos-
sible
to the IC. Figure 17 illustrates all branch currents
in
a 3-phase switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a common
ground path with any switched current paths. The left
half of the circuit gives rise to the noise generated by
a switching regulator. The ground terminations of the
synchronous MOSFETs and Schottky diodes should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP
®
compensa-
tion allows overcompensation for PC layouts which are
not
optimized but this is not the recommended design
procedure.
