22
LT1956/LT1956-5
1956f
APPLICATIO S I FOR ATIO
WUUU
oscillations. If needed, an additional capacitor (C
F
) can be
added across the R
C
/C
C
network from the V
C
pin to ground
to further suppress V
C
ripple voltage.
With a tantalum output capacitor, the LT1956 already
includes a resistor (R
C
) and filter capacitor (C
F
) at the V
C
pin (see Figures 10 and 11) to compensate the loop over
the entire V
IN
range (to allow for stable pulse skipping for
high V
IN
-to-V
OUT
ratios ≥ 4). A ceramic output capacitor
can still be used with a simple adjustment to the resistor
R
C
for stable operation (see Ceramic Capacitors section
for stabilizing LT1956). If additional phase margin is
required, a capacitor (C
FB
) can be inserted between the
output and FB pin but care must be taken for high output
voltage applications. Sudden shorts to the output can
create unacceptably large negative transients on the FB
pin.
For V
IN
-to-V
OUT
ratios < 4, higher loop bandwidths are
possible by readjusting the frequency compensation com-
ponents at the V
C
pin.
When checking loop stability, the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Proper loop compensation may be obtained
by empirical methods as described in Application Notes 19
and 76.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for ex-
ample, a battery powered device with a wall adapter input,
the output of the LT1956 can be held up by the backup
supply with the LT1956 input disconnected. In this condi-
tion, the SW pin will source current into the V
IN
pin. If the
SHDN pin is held at ground, only the shut down current of
25µA will be pulled via the SW pin from the second supply.
With the SHDN pin floating, the LT1956 will consume its
quiescent operating current of 1.5mA. The V
IN
pin will also
source current to any other components connected to the
input line. If this load is greater than 10mA or the input
could be shorted to ground, a series Schottky diode must
be added, as shown in Figure 12. With these safeguards,
the output can be held at voltages up to the V
IN
absolute
maximum rating.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 13 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, C
SS
and Q1.
As the output starts to rise, Q1 turns on, regulating switch
FREQUENCY (Hz)
GAIN (dB)
80
60
40
20
0
–20
–40
PHASE (DEG)
180
150
120
90
60
30
0
1956 F11
GAIN
PHASE
10
V
IN
= 12V
V
OUT
= 5V
I
LOAD
= 500mA
C
OUT
= 100µF, 10V, 0.1Ω
1k 10k 1M100 100k
R
C
= 2.2k
C
C
= 22nF
C
F
= 220pF
–
+
1.22V
SW
V
C
LT1956
GND
1956 F10
R1
OUTPUT
ESR
C
F
C
C
R
C
R
O
200k
ERROR
AMPLIFIER
FB
R2
C1
R
LOAD
CURRENT MODE
POWER STAGE
g
m
= 2mho
g
m
=
2000µmho
+
TANTALUM
ESL
C1
CERAMIC
C
FB
Figure 10. Model for Loop Response Figure 11. Overall Loop Response
