SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 20 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits and the parity are selected by writing the
appropriate bits in this register.
Table 13. Interrupt Status Register bits description
Bit Symbol Description
7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC16C2550B mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] not used
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2 and 3 (see
Table 12).
logic 0 or cleared = default condition
0 ISR[0] INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Table 14. Line Control Register bits description
Bit Symbol Description
7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6 LCR[6] Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3 LCR[5:3] Programs the parity conditions (see
Table 15)
2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see
Table 16).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 17).
logic 0 or cleared = default condition
Table 15. LCR[5:3] parity selection
LCR[5] LCR[4] LCR[3] Parity selection
X X 0 no parity
X 0 1 odd parity
0 1 1 even parity
0 0 1 forced parity ‘1’
1 1 1 forced parity ‘0’