SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 28 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Fig 9. General read timing
data
active
active
valid
address
002aae278
A0 to A2
CSA, CSB
IOR
D0 to D7
t
12d
t
12h
t
7d
t
7w
t
9d
t
6h
t
7h
t
6s
Fig 10. Modem input/output timing
t
17d
change of state
t
18d
t
18d
t
19d
002aae277
t
18d
change of state
change of state change of state
active
active active active
active active active
change of state
RTSA, RTSB
DTRA, DTRB
IOW
CDA, CDB
CTSA, CTSB
DSRA, DSRB
INTA, INTB
IOR
RIA, RIB
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 29 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Fig 11. External clock timing
EXTERNAL
CLOCK
002aaa112
t
w3
t
w2
t
w1
f
XTAL
1
t
w3
-------
=
Fig 12. Receive timing
D0 D1 D2 D3 D4 D5 D6 D7
active
active
16 baud rate clock
002aae276
RXA, RXB
INTA, INTB
IOR
t
21d
t
20d
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next
data
start
bit
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 30 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Fig 13. Receive ready timing in non-FIFO mode
D0 D1 D2 D3 D4 D5 D6 D7
002aae275
next
data
start
bit
stop
bit
parity
bit
t
25d
RXn
RXRDYn
IOR
active data
ready
start
bit
data bits (0 to 7)
active
t
26d
Fig 14. Receive ready timing in FIFO mode
D0 D1 D2 D3 D4 D5 D6 D7
002aae274
first byte that
reaches the
trigger level
stop
bit
parity
bit
t
25d
RXA, RXB
RXRDYA, RXRDYB
IOR
active data
ready
start
bit
data bits (0 to 7)
active
t
26d

SC16C2550BIBS,128

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 16CB 2.5V-5V 2CH
Lifecycle:
New from this manufacturer.
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