USBLC6-2 Technical information
Doc ID 11265 Rev 5 7/14
Figure 12. Analog crosstalk measurements
Figure 12. shows the measurement circuit for the analog application. In usual frequency
range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see
Figure 13.).
Figure 13. Analog crosstalk results
As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The frequency response (Figure 5.) gives attenuation
information and shows that the USBLC6-2 is well suitable for data line transmission up to
480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies,
for instance.
NETWORK ANALYSER
PORT 2
NETWORK ANALYSER
PORT 1
TEST BOARD
Vbus
USBL
C6
-2SC6
100.0k 1.0M 10.0M 100.0M 1.0G
- 120.00
- 90.00
- 60.00
- 30.00
0.00
dB
F (Hz)
Technical information USBLC6-2
8/14 Doc ID 11265 Rev 5
2.5 Application examples
Figure 14. USB 2.0 port application diagram using USBLC6-2
Figure 15. T1/E1/Ethernet protection
HUB-
DOWNSTREAM
TRANSCEIVER
+ 5V
R
S
R
S
R
S
R
S
R
PD
R
PD
R
PD
R
PD
Protecting
Bus Switch
DEVICE-
UPSTREAM
TRANSCEIVER
+ 3.3V
SW
1
R
PU
V
BUS
D+
D-
GND
V
BUS
V
BUS
V
BUS
R
X LS/FS
+ R
X LS/FS
+
R
X LS/FS
+
R
X LS/FS
+
R
X HS
+ R
X HS
+
R
X HS
+
R
X HS
+
T
X HS
+ T
X HS
+
T
X HS
+
T
X HS
+
T
X LS/FS
+ T
X LS/FS
+
T
X LS/FS
+
T
X LS/FS
+
R
S
R
S
USB
connector
T
X LS/FS -
T
X LS/FS -
T
X LS/FS -
T
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X LS/FS -
R
X HS -
R
X HS -
R
X HS -
R
X HS -
T
X HS -
T
X HS -
T
X HS -
T
X HS -
GND GND
GND
GND
SW
2
DEVICE-
UPSTREAM
TRANSCEIVER
USBLC6-4SC6
USBLC6-2P6
USBLC6-2SC6
+ 3.3V
SW
1
R
PU
V
BUS
D+
D-
GND
R
S
R
S
USB
connector
SW
2
OpenClosed then openHigh Speed HS
OpenClosedFull Speed FS
ClosedOpenLow Speed LS
SW
2
SW
1
Mode
DATA
TRANSCEIVER
SMP75-8
SMP75-8
Tx
Rx
+V
CC
+V
CC
100nF
100nF
USBLC6-2SC6USBLC6-2SC6
USBLC6-2 Technical information
Doc ID 11265 Rev 5 9/14
2.6 PSpice model
Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are
defined by the PSpice parameters given in Figure 17.
Figure 16. PSpice model
Note: This simulation model is available only for an ambient temperature of 27 °C.
MODEL = Dlow MODEL = Dhigh
VBUS
LI/O
LGND
GND
D+in
MODEL = Dzener
RI/O
LI/O
D-in
RI/O
LI/O
LI/O
RGND RI/O
D-out
RI/O
MODEL = Dlow MODEL = Dhigh
LI/O
D+out
RI/O
Figure 17. PSpice parameters Figure 18. USBLC6-2 PCB layout
considerations
Dlow Dhigh Dzener
BV 50 50 7.3
CJ0 0.9p 2.0p 40p
IBV 1m 1m 1m
M 0.3333 0.3333 0.3333
RS 0.2 0.52 0.84
VJ 0.6 0.6 0.6
TT 0.1u 0.1u 0.1u
LI/O 750p
RI/O 110m
LGND 550p
RGND 60m
D+in
D+out
D-out
GND
USBLC6-2
D-in
V
BUS
1
C = 100nF
BUS

USBLC6-2SC6

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
TVS Diodes / ESD Suppressors ESD Protection Low Cap
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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