VNN7NV04P-E, VNS7NV04P-E Electrical specifications
Doc ID 15632 Rev 4 7/29
2.2 Thermal data
2.3 Electrical characteristics
-40 °C < T
j
< 150 °C, unless otherwise specified.
Table 3. Thermal data
Symbol Parameter
Value
Unit
SOT-223 SO-8
R
thj-case
Thermal resistance junction-case max 18 °C/W
R
thj-lead
Thermal resistance junction-lead max 27 °C/W
R
thj-amb
Thermal resistance junction-ambient max 96
(1)
1. When mounted on a standard single-sided FR4 board with 0.5 mm
2
of Cu (at least 35 µm thick) connected
to all DRAIN pins.
90
(1)
°C/W
Table 4. Electrical characteristics
Symbol Parameter Test conditions Min Typ Max Unit
Off
V
CLAMP
Drain-source clamp
voltage
V
IN
=0V; I
D
= 3.5 A 40 45 55 V
V
CLTH
Drain-source clamp
threshold voltage
V
IN
=0V; I
D
=2mA 36 V
V
INTH
Input threshold voltage V
DS
=V
IN
; I
D
=1mA 0.5 2.5 V
I
ISS
Supply current from input
pin
V
DS
=0V; V
IN
= 5 V 100 150 µA
V
INCL
Input-source clamp
voltage
I
IN
=1mA 6 6.8 8 V
I
IN
= -1 mA -1.0 -0.3 V
I
DSS
Zero input voltage drain
current (V
IN
=0V)
V
DS
=13V; V
IN
=0V; T
j
=2C 30 µA
V
DS
=25V; V
IN
=0V 75 µA
On
R
DS(on)
Static drain-source on
resistance
V
IN
=5V; I
D
= 3.5 A; T
j
=2C 65 mΩ
V
IN
=5V; I
D
= 3.5 A 130 mΩ
Dynamic (T
j
= 25 °C, unless otherwise specified)
g
fs
(1)
Forward
transconductance
V
DD
=13V; I
D
=3.5A 9 S
C
OSS
Output capacitance V
DS
=13V; f=1MHz; V
IN
= 0 V 220 pF
Electrical specifications VNN7NV04P-E, VNS7NV04P-E
8/29 Doc ID 15632 Rev 4
Switching
(T
j
= 25 °C, unless otherwise specified)
t
d(on)
Turn-on delay time
V
DD
=15V; I
D
=3.5A;
V
gen
=5V; R
gen
=R
IN MIN
= 150 Ω;
(see figure Figure 4)
100 300 ns
t
r
Rise time 470 1500 ns
t
d(off)
Turn-off delay time 500 1500 ns
t
f
Fall time 350 1000 ns
t
d(on)
Turn-on delay time
V
DD
=15V; I
D
=3.5A;
V
gen
=5V; R
gen
=2.2KΩ;
(see figure Figure 4)
0.75 2.3 µs
t
r
Rise time 4.6 14.0 µs
t
d(off)
Turn-off delay time 5.4 16.0 µs
t
f
Fall time 3.6 11.0 µs
(dI/dt)
on
Turn-on current slope
V
DD
=15V; I
D
= 3.5 A; V
gen
=5V;
R
gen
=R
IN MIN
=150Ω
6.5 A/µs
Q
i
Total input charge
V
DD
=12V; I
D
= 3.5 A; V
IN
=5V;
I
gen
= 2.13 mA (see figure Figure 7)
18 nC
Source drain diode (T
j
= 25 °C, unless otherwise specified)
V
SD
(1)
Forward on voltage I
SD
= 3.5 A; V
IN
=0V 0.8 V
t
rr
Reverse recovery time
I
SD
= 3.5 A; dI/dt = 20 A/µs;
V
DD
=30V; L=20H;
(see test circuit, figure Figure 5)
220 ns
Q
rr
Reverse recovery charge 0.28 µC
I
RRM
Reverse recovery current 2.5 A
Protections (-40 °C < T
j
< 150 °C, unless otherwise specified)
I
lim
Drain current limit V
IN
=5V; V
DS
=13V 6 9 12 A
t
dlim
Step response current
limit
V
IN
=5V; V
DS
=13V 4.0 µs
T
jsh
Overtemperature
shutdown
150 175 200 °C
T
jrs
Overtemperature reset 135 °C
I
gf
Fault sink current V
IN
=5V; V
DS
=13V; T
j
=T
jsh
15 mA
E
as
Single pulse avalanche
energy
starting T
j
=2C; V
DD
=24V; V
IN
=5V;
R
gen
=R
IN MIN
=150Ω; L = 24 mH;
(see Figure 6 and Figure 8)
200 mJ
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
Table 4. Electrical characteristics (continued)
Symbol Parameter Test conditions Min Typ Max Unit
VNN7NV04P-E, VNS7NV04P-E Protection features
Doc ID 15632 Rev 4 9/29
3 Protection features
During normal operation, the input pin is electrically connected to the gate of the internal
Power MOSFET through a low impedance path.
The device then behaves like a standard Power MOSFET and can be used as a switch from
DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current
I
ISS
(typ. 100µA) flows into the input pin in order to supply the internal circuitry.
The device integrates:
Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche
characteristics of the Power MOSFET stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly important when driving inductive
loads.
Linear current limiter circuit: limits the drain current I
D
to I
lim
whatever the input pin
voltages. When the current limiter is active, the device operates in the linear region, so
power dissipation may exceed the capability of the heatsink. Both case and junction
temperatures increase, and if this phase lasts long enough, junction temperature may
reach the overtemperature threshold T
jsh
.
Overtemperature and short circuit protection: these are based on sensing the chip
temperature and are not dependent on the input voltage. The location of the sensing
element on the chip in the power stage area ensures fast, accurate detection of the
junction temperature. Overtemperature cutout occurs in the range 150 to 190 °C, a
typical value being 170 °C. The device is automatically restarted when the chip
temperature falls of about 15 °C below shutdown temperature.
Status feedback: in the case of an overtemperature fault condition (T
j
> T
jsh
), the device
tries to sink a diagnostic current I
gf
through the input pin in order to indicate fault
condition. If driven from a low impedance source, this current may be used in order to
warn the control circuit of a device shutdown. If the drive impedance is high enough so
that the input pin driver is not able to supply the current I
gf
, the input pin falls to 0 V. This
however not affects the device operation: no requirement is put on the current capability
of the input pin driver except to be able to supply the normal operation drive current
I
ISS
.
Additional features of this device are ESD protection according to the Human Body model
and the ability to be driven from a TTL logic circuit.

VNN7NV04PTR-E

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Gate Drivers 40V 6A OMNIFET
Lifecycle:
New from this manufacturer.
Delivery:
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