NCP81253
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9
in the electrical characteristics table in this datasheet. Setting
the voltage on EN to a mid−state level will pull both DRVH
and DRVL low. Refer to Table 6 for the EN/PWM logic
table.
Setting EN to the mid−state level can be used for body
diode braking to quickly reduce the inductor current. By
turning the LS FET off and having the current conduct
through the LS FET body diode, the voltage at the switch
node will be at a greater negative potential compared to
having the LS FET on. This greater negative potential on
switch node allows there to be a greater voltage across the
output inductor, since the opposite terminal of the inductor
is connected to the converter output voltage. The larger
voltage across the inductor causes there to be a greater
inductor current slew rate, allowing the current to decrease
at a faster rate.
Three−State PWM Input
Switching PWM between logic−high and logic−low states
will allow the driver to operate in continuous conduction
mode as long as VCC is greater than the UVLO threshold
and EN is high. The threshold limits are specified in the
electrical characteristics table in this datasheet. Refer to
Figure 15 for the gate timing diagrams and Table 6 for the
EN/PWM logic table.
When PWM is set above PWM
HI
, DRVL will first turn off
after a propagation delay of tpdl
DRVL
. To ensure
non−overlap between DRVL and DRVH, there is a delay of
tpdh
DRVH
from the time DRVL falls to 1 V, before DRVH is
allowed to turn on.
When PWM falls below PWM
LO
, DRVH will first turn
off after a propagation delay of tpdl
DRVH
. To ensure
non−overlap between DRVH and DRVL, there is a delay of
tpdh
DRVL
from the time DRVH – SW falls to 1 V, before
DRVL is allowed to turn on.
When PWM enters the mid−state voltage range (and
thereby exiting the logic high or logic low states), both
DRVH and DRVL are pulled low for the non−overlap delay
(tpdh). If PWM is still in the mid−state at the conclusion of
the non−overlap delay, both DRVH and DRVL will remain
in the off states.
To minimize power consumption when the NCP81253 is
in a disabled state, the internal voltage rails that determine
the low/mid/high PWM logic states are shut down when EN
is low. When EN is brought high (while VCC is above the
UVLO threshold), the PWM internal voltage rails are
brought up, but require some time to rise to their proper
levels. To prevent a PWM signal from being interpreted
incorrectly during this time, there is a delay from EN rising
to the driver responding to PWM signals, which is set at a
typical value of 50 ms.
Table 6. EN/PWM LOGIC TABLE
EN PWM DRVH DRVL
LOW X LOW LOW
HIGH LOW LOW HIGH
HIGH MID LOW LOW
HIGH HIGH HIGH LOW
MID LOW LOW LOW
MID MID LOW LOW
MID HIGH LOW LOW
Thermal Considerations
As power in the NCP81253 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCP81253 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCP81253 can handle is given by:
P
D(MAX)
+
ƪ
T
J(MAX)
* T
A
ƫ
R
qJA
(eq. 1)
Since T
J
is not recommended to exceed 150°C, the
NCP81253, soldered on to a 645 mm
2
copper area, using
1 oz. copper and FR4, can dissipate up to 1.05 W when the
ambient temperature (T
A
) is 25°C. The power dissipated by
the NCP81253 can be calculated from the following
equation:
P
D
[ VCC @
ƪ
(n
HS
@ Qg
HS
) n
LS
@ Qg
LS
) @ f ) I
standby
ƫ
(eq. 2)
Where n
HS
and n
LS
are the number of high−side and
low−side FETs, respectively, Qg
HS
and Qg
LS
are the gate
charges of the high−side and low−side FETs, respectively
and f is the switching frequency of the converter.
