NOT RECOMMENDED FOR
NEW DESIGNS
6.42
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
12
FEBRUARY 15, 2008
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)
(2,3)
(VDD = 1.8V ± 100mV, TA = 0°C to +70°C)
NOTES:
1. The Pipelined output parameters (t
CYC2, tCD2) apply to either or both left and right ports when PL/FTX = VDD (1.8V). Flow-through parameters (tCYC1, tCD1) apply
when PL/FT = V
SS (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and PL/FT. PL/FT should be treated as DC
signals, i.e. steady state during operation.
3. These values are valid for any level of V
DDQ (3.3V/2.5V/1.8V).
4. Guaranteed by design (not production tested).
70P3519/99
S200
Com'l Only
70P3519/99
S166
Com'l & Ind
Symbol Parameter Min.Max.Min.Max.Unit
t
CYC1
Clock Cycle Time (Flow-Through)
(1)
15
____
20
____
ns
t
CYC2
Clock Cycle Time (Pipelined)
(1)
5
____
6
____
ns
t
CH1
Clock High Time (Flow-Through)
(1)
6
____
8
____
ns
t
CL1
Clock Low Time (Flow-Through)
(1)
6
____
8
____
ns
t
CH2
Clock High Time (Pipelined)
(2)
2
____
2.4
____
ns
t
CL2
Clock Low Time (Pipelined)
(1)
2
____
2.4
____
ns
t
SA
Address Setup Time 1.5
____
1.7
____
ns
t
HA
Address Hold Time 0.5
____
0.5
____
ns
t
SC
Chip Enable Setup Time 1.5
____
1.7
____
ns
t
HC
Chip Enable Hold Time 0.5
____
0.5
____
ns
t
SB
Byte Enable Setup Time 1.5
____
1.7
____
ns
t
HB
Byte Enable Hold Time 0.5
____
0.5
____
ns
t
SW
R/W Setup Time 1.5
____
1.7
____
ns
t
HW
R/W Hold Time 0.5
____
0.5
____
ns
t
SD
Input Data Setup Time 1.5
____
1.7
____
ns
t
HD
Input Data Hold Time 0.5
____
0.5
____
ns
t
SAD
ADS Setup Time
1.5
____
1.7
____
ns
t
HAD
ADS Hold Time
0.5
____
0.5
____
ns
t
SCN
CNTEN Setup Time
1.5
____
1.7
____
ns
t
HCN
CNTEN Hold Time
0.5
____
0.5
____
ns
t
SRPT
REPEAT Setup Time
1.5
____
1.7
____
ns
t
HRPT
REPEAT Hold Time
0.5
____
0.5
____
ns
t
OE
Output Enable to Data Valid
____
4.4
____
4.4 ns
t
OLZ
(4)
Output Enable to Output Low-Z 1
____
1
____
ns
t
OHZ
(4)
Output Enable to Output High-Z 1 3.4 1 3.6 ns
t
CD1
Clock to Data Valid (Flow-Through)
(1)
____
10
____
12 ns
t
CD2
Clock to Data Valid (Pipelined)
(1)
____
3.4
____
3.6 ns
t
DC
Data Output Hold After Clock High 1
____
1
____
ns
t
CKHZ
(4)
Clock High to Output High-Z 1 3.4 1 3.6 ns
t
CKLZ
(4)
Clock High to Output Low-Z 1
____
1
____
ns
t
INS
Interrupt Flag Set Time
____
7
____
7ns
t
INR
Interrupt Flag Reset Time
____
7
____
7ns
t
COLS
Collision Flag Set Time
____
3.4
____
3.6 ns
t
COLR
Collision Flag Reset Time
____
3.4
____
3.6 ns
t
ZZSC
Sleep Mode Set Cycles 2
____
2
____
cycles
t
ZZRC
Sleep Mode Recovery Cycles 3
____
3
____
cycles
Port-to-Port Delay
t
CO
Clock-to-Clock Offset 4
____
5
____
ns
t
OFS
Clock-to-Clock Offset for Collision Detection
Please refer to Collision Detection Timing Table
on Page 21
7144 tbl 11
