NOT RECOMMENDED FOR
NEW DESIGNS
6.42
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
6
FEBRUARY 15, 2008
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE
0
CE
1
BE
3
BE
2
BE
1
BE
0
R/W ZZ
Byte 3
I/O
27-35
Byte 2
I/O
18-26
Byte 1
I/O
9-17
Byte 0
I/O
0-8
MODE
X ↑ HXXXXXXLHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X ↑ XLXXXXXLHigh-ZHigh-ZHigh-ZHigh-ZDeselected–Power Down
X ↑ LHHHHHX LHigh-ZHigh-ZHigh-ZHigh-ZAll Bytes Deselected
X ↑ LHHHHL L LHigh-ZHigh-ZHigh-Z D
IN
Write to Byte 0 Only
X ↑ L H H H L H L L High-Z High-Z D
IN
High-Z Write to Byte 1 Only
X ↑ LHHLHHLLHigh-Z D
IN
High-Z High-Z Write to Byte 2 Only
X ↑ LHLHHHLL D
IN
High-Z High-Z High-Z Write to Byte 3 Only
X ↑ L H H H L L L L High-Z High-Z D
IN
D
IN
Write to Lower 2 Bytes Only
X ↑ LHLLHHLL D
IN
D
IN
High-Z High-Z Write to Upper 2 bytes Only
X ↑ LHLLLLLL D
IN
D
IN
D
IN
D
IN
Write to All Bytes
L ↑ LHHHHLHLHigh-ZHigh-ZHigh-Z D
OUT
Read Byte 0 Only
L ↑ L H H H L H H L High-Z High-Z D
OUT
High-Z Read Byte 1 Only
L ↑ LHHLHHHLHigh-ZD
OUT
High-Z High-Z Read Byte 2 Only
L ↑ LHLHHHHL D
OUT
High-Z High-Z High-Z Read Byte 3 Only
L ↑ L H H H L L H L High-Z High-Z D
OUT
D
OUT
Read Lower 2 Bytes Only
L ↑ LHLLHHHL D
OUT
D
OUT
High-Z High-Z Read Upper 2 Bytes Only
L ↑ LHLLLLHL D
OUT
D
OUT
D
OUT
D
OUT
Read All Bytes
H ↑ XXXXXXX LHigh-ZHigh-ZHigh-ZHigh-ZOutputs Disabled
XXXXXXXXXHHigh-ZHigh-ZHigh-ZHigh-ZSleep Mode
7144 tbl 02
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE
0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
0, CE1 and BEn
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS
(4)
CNTEN
(5)
REPEAT
(4,6)
I/O
(3)
MODE
An X An ↑ LX H D
I/O
(n) External Address Used
XAnAn + 1↑ H L H D
I/O
(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1 ↑ HH HD
I/O
(n+1) External Address Blocked—Counter disabled (An + 1 reused)
XXAn↑ XX L D
I/O
(n) Counter Set to last valid ADS load
7144 tbl 03
