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70P3519S166BCG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NOT RECOMMENDED FOR
NEW DESIGNS
6.42
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
13
An An + 1 An + 2 An + 3
t
CYC2
t
CH2
t
CL2
R/
W
ADDRESS
CE
0
CLK
CE
1
BE
n
(3)
DATA
OUT
OE
t
CD2
t
CKLZ
Qn Qn+1 Qn+2
t
OHZ
t
OLZ
t
OE
7144 drw 05
(1)
(1)
t
SC
t
HC
t
SB
t
HB
t
SW
t
HW
t
SA
t
HA
t
DC
t
SC
t
HC
t
SB
t
HB
(4)
(1 Latency)
(5)
(5)
,
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE
'X'
= V
IH
)
(1,2)
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = V
IL
, CNTEN and REPEAT = V
IH
.
3. The output is disabled (High-Impedance state) by CE
0
= V
IH
, CE
1
= V
IL
, BE
n
= V
IH
following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = V
IL
constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BE
n
was HIGH, then the appropriate Byte of DATA
OUT
for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE
"X"
= V
IL
)
(1,2,6)
An An + 1 An + 2 An + 3
t
CYC1
t
CH1
t
CL1
R/
W
ADDRESS
DATA
OUT
CE
0
CLK
OE
t
SC
t
HC
t
CD1
tCKLZ
Qn Qn + 1
Qn + 2
tOHZ
tOLZ
tOE
t
CKHZ
7144 drw 06
(5)
(1)
CE
1
BEn
(3)
tSB tHB
t
SW
t
HW
t
SA
t
HA
t
DC
t
DC
(4)
t
SC
t
HC
tSB
tHB
,
NOT RECOMMENDED FOR
NEW DESIGNS
6.42
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
14
FEBRUARY 15, 2008
,
t
SC
t
HC
CE
0(B1)
A
DDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
A
DDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
t
SC
t
HC
t
CKHZ
t
CKLZ
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
7144 drw 07
Timing Waveform of a Multi-Device Pipelined Read
(1,2)
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70P3519/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS
(B1) = ADDRESS(B2) in this situation.
2. BE
n, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
Timing Waveform of a Multi-Device Flow-Through Read
(1,2)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
H
A
CLK
7144 drw 08
D
0
D
3
t
CD1
t
CKLZ
t
CKHZ
(1)
(1)
D
1
DATA
OUT(B1)
t
CH1
t
CL1
t
CYC1
(1)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
D
2
D
4
t
CD1
t
CD1
t
CKHZ
t
DC
t
CD1
t
CKLZ
t
SC
t
HC
(1)
t
CKHZ
(1)
t
CKLZ
(1)
t
CD1
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
D
5
t
CD1
t
CKLZ
(1)
t
CKHZ
(1)
NOT RECOMMENDED FOR
NEW DESIGNS
6.42
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
15
CLK
"A"
R/W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
NO
MATCH
VALID
NO
MATCH
MATCH
MATCH
VALID
7144 drw 09
t
DC
,
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
NOTES:
1. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = V
IL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If t
CO
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t
CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be t
CO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,4)
DATA
IN "A"
CLK
"B"
R/W
"B"
ADDRESS
"A"
R/W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CD1
t
DC
DATA
OUT "B"
7144 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
CD1
t
CO
tDC
tSA
tSW
tHA
(3)
,
NOTES:
1. CE
0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If t
CO
< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
t
CO
+ t
CYC
+ t
CD1
). If t
CO
> minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be t
CO
+ t
CD1
).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

70P3519S166BCG8

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Buy 70P3519S166BCG8
Manufacturer:
Description:
IC SRAM 9M PARALLEL 256CABGA
Lifecycle:
New from this manufacturer.
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