NCP6915
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7
Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for T
J
up to +125°C unless otherwise specified.
PVIN = V
IN1
= V
IN2
= 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical
values are referenced to T
J
= + 25°C and default configuration (Note 7).
Symbol UnitMaxTypMinConditionsParameter
HWEN
I
EN
0.1 1
mA
I
2
C
V
I2C
Voltage at SCL and SDA line 1.7 5.0 V
V
I2CIL
SCL, SDA low input voltage SCL, SDA pin (Note 6) 0.5 V
V
I2CIH
SCL, SDA high input voltage SCL, SDA pin (Note 6) 0.8 x
V
I2
CC
V
V
I2COL
SCL, SDA low output voltage I
SINK
= 3 mA (Note 8) 0.4 V
F
SCL
I
2
C clock frequency (Note 8) 3.4 MHz
TOTAL DEVICE
V
UVLO
Under Voltage Lockout V
IN
falling 2.3 V
V
UVLOH
Under Voltage Lockout Hysteresis V
IN
rising 60 200 mV
T
SD
Thermal Shut Down Protection 150 °C
T
WARNING
Warning Rising Edge 135 °C
T
SDR
Thermal Shut Down Rearming 110 °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Devices that use non−standard supply voltages which do not conform to the intent I
2
C bus system levels must relate their input levels
to the V
DD
voltage to which the pull−up resistors R
P
are connected.
7. Refer to the Application Information section of this data sheet for more details.
8. Guaranteed by design and characterized.
NCP6915
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8
DETAILED DESCRIPTION
The NCP6915 is optimized to supply the different sub
systems of battery powered portable applications. The IC
can be supplied directly from the latest technology single
cell batteries such as Lithium−Polymer as well as from triple
alkaline cells. Alternatively, the IC can be supplied from a
pre−regulated supply rail in case of multi−cell or mains
powered applications.
The output voltage range, current capabilities and
performance of the switched mode DCDC converter are
well suited to supply the different peripherals in the system
as well as to supply processor cores. To reduce overall power
consumption of the application, Dynamic Voltage Scaling
(DVS) is supported on the DCDC converter. For PWM
operation, the converter runs on a local 3 MHz clock. A low
power PFM mode is provided that ensures that even at low
loads high efficiency can be obtained. All the switching
components are integrated including the compensation
networks and synchronous rectifier. Small sized 1 uH
inductor and 10 uF bypass capacitor are required for typical
applications.
The general purpose low dropout regulators can be used
to supply the lower power rails in the application. To
improve on overall application standby current, the bias
current of these regulators are made very low. The regulators
have two separated input supply pin to be able to connect
them independently to either the system supply voltage or to
the output of the DCDC converter in the application. The
regulators are bypassed with a small size 1.0 uF capacitor.
The IC is controlled through the I
2
C interface that allows
to program amongst others the output voltages of the
different supply rails as well as to configure its behavior. In
addition to this bus, a digital hardware enable control pin
(HWEN) is provided.
Under Voltage Lockout
The core does not operate for voltages below the under
voltage lockout (UVLO) threshold and all internal circuitry,
both analog and digital, is held in reset.
NCP6915 functionality is guaranteed down to V
UVLO
when the battery is falling. A hysteresis is implemented to
avoid erratic on / off behavior of the IC. Due to its 200 mV
hysteresis, when the battery is rising, re−start is guaranteed
at 2.5 V.
Thermal Shutdown
Given the output power capabilities of the on chip step
down converters and low drop out regulators the thermal
capabilities of the device can be exceeded. A thermal
protection circuit is therefore implemented to prevent the
part from damage. This protection circuit is only activated
when the core is in active mode (at least one output channel
is enabled). During thermal shutdown, all outputs of
NCP6915 are off.
When NCP6915 returns from thermal shutdown, it can
re−start in two different configurations depending on
REARM[7:6] bits ($09 register). If REARM[7:6] = 00 then
NCP6915 re−starts with default register values, otherwise it
re−starts with register values set prior to thermal shutdown.
In addition, a thermal warning is implemented which can
inform the processor through an interrupt that NCP6915 is
close to its thermal shutdown so that preventive action can
be taken by software.
Active Output Discharge
By default, to prevent any disturbances on power−up
sequence, output discharge is activated as soon as the input
voltage is valid (upper than UVLO+ hyst).
After power up sequence and during ON state, output
discharge can be independently enabled / disabled by
appropriate settings in the DIS register (refer to the register
definition section).
If a power down sequence, UVLO or thermal shutdown
events occur, the output discharge paths are activated until
the next PUS and ON state.
When the IC is turned off when VIN1 drops down below
UVLO threshold, no shut down sequence is expected, all
supplies are disabled and outputs turn to high impedance.
Enabling
The HWEN pin controls the device start up. If HWEN is
raised, this starts the power up sequencer (PUS). If HWEN
is made low, device enters in shutdown mode and all
regulators will be turned off with inverted PUS of power up.
A built−in pull−down resistor disables the device if this
pin is left unconnected.
When HWEN is high, the different power rails can be
independently enabled / disabled by writing the appropriate
bit in the ENABLE register.
Power Up Sequence and HWEN
When enabling part with HWEN pin, the part will be set
with the default configuration factory programmed in the
registers, if no I
2
C programming has been done as described
in the below table.
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Table 5. DEFAULT POWER UP SEQUENCER
Delay (in ms) from Tstart
Sequence Default Assignment Default Vprog
Default Mode and
ON/OFF
128 To: 000 DCDC 1.20 V Auto PFM/PWM OFF
256 T1: 001 LDO1 2.80 V OFF
512 T2: 011 LDO2 2.80 V OFF
640 T3: 100 LDO3 1.80 V OFF
768 T4: 101 LDO4 2.80 V OFF
896 T5: 110 LDO5 1.80 V OFF
NOTE: Additional power sequence are available. Please contact your ON Semiconductor representative for further information.
Figure 2. IPUS
The initial power up sequence (IPUS) is described in
Figure 2.
Remark 1: T2 – T1 = 2x 128 ms in the default configuration.
Can be reprogrammed at 128 ms by I
2
C.
Remark 2: LDOs must be turned on sequentially to avoid
inrush current on Vin source. So it’s strongly recommended
to turn them one by one, even if the default PUS sequence
is changed by I
2
C.
O
F
F
M
O
D
E
POR
UVLO
HWEN
(DCDC_T[2:0] + 1) x
128
ms
*
DVS ramp
Time
600 us
typ
VIN1, VIN2
VOUT DCDC
Soft start90%
Bias
Time
(LDOx_T[2:0] + 1) x
128
ms
*
VOUT LDOx
128 us
I@C
Figure 3. IPUS
In order to power up the circuit, the input voltage VIN1
has to rise above the VUVLO threshold. This triggers the
internal core circuitry power up including:
Internal references
Core circuitry “Wake Up Time”
DCDC “Bias Time”
These delays are internals and cannot be bypassed.

NCP6915AFCCLT1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators USR 1DCDC 5LDO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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