LTM4632
13
4632fb
For more information www.linear.com/LTM4632
APPLICATIONS INFORMATION
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented,
and
a
graph is displayed representing the RMS ripple current
reduction as a function of the number of interleaved
phases. Figure 4 shows this graph.
Channel 1 Output Voltage Tracking and Soft-Start
The TRACK/SS pin provides a means to either soft-start
the Channel 1 regulator or track it to a different power
supply. A capacitor on the TRACK/SS pin will program
the ramp rate of the channel 1 output voltage. An internal
1.2µA current source will charge up the external soft-start
capacitor towards INTV
CC
voltage. When the TRACK/SS
voltage is below 0.6V, it will take over the internal 0.6V
reference voltage to control the output voltage. The total
soft-start time can be calculated as:
t
SS
=0.6
C
SS
1.2µA
where C
SS
is the capacitance on the TRACK/SS pin. Forced
continuous mode are disabled during the soft-start process.
Channel 1 output voltage tracking can also be programmed
externally using the TRACK/SS pin. The output can be
tracked up and down with another regulator. Figure 5 and
Figure 6 show an example waveform and schematic of a
Ratiometric tracking where the slave regulators output
slew rate is proportional to the master’s.
Since the slave regulators TRACK/SS is connected to
the masters output through a R
TR(TOP)
/R
TR(BOT)
resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
output voltage and the master output voltage should satisfy
the following equation during the start-up.
V
OUT(SL)
R
FB(SL)
R
FB(SL)
+60.4k
=
V
OUT(MA)
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
The R
FB(SL)
is the feedback resistor and the R
TR(TOP)
/
R
TR(BOT)
is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 6.
Following the upper equation, the masters output slew
rate (MR) and the slaves output slew rate (SR) in Volts/
Time is determined by:
MR
SR
=
R
FB(SL)
R
FB(SL)
+60.4k
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
For example, V
OUT(MA)
= 1.5V, MR = 1.5V/1ms and
V
OUT(SL)
= 1.2V, SR = 1.2V/1ms. From the equation, we
could solve out that R
TR(TOP)
= 60.4k and R
TR(BOT)
= 40.2k
is a good combination for the Ratiometric tracking.
TIME
SLAVE OUTPUT
MASTER OUTPUT
OUTPUT VOLTAGE
4632 F05
Figure 5. Output Ratiometric Tracking Waveform
The TRACK pins will have the 1.2µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
LTM4632
14
4632fb
For more information www.linear.com/LTM4632
APPLICATIONS INFORMATION
The Coincident output tracking can be recognized as a
special Ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slaves output
slew rate (SR), as waveform shown in Figure 7.
From the equation, we could easily find out that, in the
Coincident tracking, the slave regulators TRACK/SS pin
resistor divider is always the same as its feedback divider.
R
FB(SL)
R
FB(SL)
+60.4k
=
R
TR(BOT)
R
TR(TOP)
+R
TR(BOT)
V
IN
V
OUT1
V
OUT2
VTTR
FB1
GND
LTM4632
COMP1
COMP2
INTV
CC
V
IN
3.6V TO 15V RAIL
V
OUT1
1.5V, 3A
10µF
16V
0.1µF
22µF
4V
RUN1
40.2k
PGOOD1 PGOOD2
RUN2
SYNC/MODE
TRACK/SS1
V
DDQIN
V
IN
V
OUT1
V
OUT2
VTTR
FB1
GND
LTM4632
COMP1
COMP2
INTV
CC
V
OUT2
1.2V, 3A
22µF
4V
RUN1
60.4k
4632 F06
40.2k
60.4k
V
OUT1
PGOOD1 PGOOD2
RUN2
SYNC/MODE
TRACK/SS1
V
DDQIN
Figure 6. Example Schematic of Ratiometric Output Voltage Tracking
TIME
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT VOLTAGE
4632 F07
Figure 7. Output Coincident Tracking Waveform
LTM4632
15
4632fb
For more information www.linear.com/LTM4632
APPLICATIONS INFORMATION
For example, R
TR(TOP)
= 60.4k and R
TR(BOT)
= 60.4k is a
good combination for Coincident tracking for V
OUT(MA)
=
1.5V and V
OUT(SL)
= 1.2V application.
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a ±8% window around the regulation point. A resistor can
be pulled up to a particular supply voltage for monitoring.
To prevent unwanted PGOOD glitches during transients
or dynamic V
OUT
changes, the LTM4632’s PGOOD falling
edge includes a blanking delay of approximately 40us.
Stability Compensation
The LTM4632 module internal compensation loop is
de-signed and optimized for low ESR ceramic output
capacitors only application. Table 5 is provided for most
application requirements. The LTpowerCAD Design Tool is
available to download for control loop analysis for further
optimization.
RUN Enable
Pulling the RUN pin to ground forces the LTM4632 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Tying the RUN pin
voltage above 1.28V will turn on the entire chip.
Low Input Application
The LTM4632 is capable to run from 3.3V input when
the V
IN
pin is tied to INTV
CC
pin. See Figure 21 for the
application circuit. Please note the INTV
CC
pin has 3.6V
abs max voltage rating.
Pre-Biased Output Start-Up (Channel 1)
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4632 channel 1 can safely power
up into a pre-biased output without discharging it.
The LTM4632 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS1 pin voltage
reaches 80% of the 0.6V reference voltage for channel 1.
This will prevent the BG from turning on during the pre-
biased output start-up which would discharge the output.
Do not pre-bias LTM4632 with a voltage higher than INTV
CC
(3.3V) voltage.
Overtemperature Protection
The internal overtemperature protection monitors the junc
-
tion temperature of the module. If
the junction temperature
reaches approximately 170°C, both power switches will be
turned off until the temperature drops about 10°C cooler.
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTM4632 constantly
monitors each V
IN
pin for an overvoltage condition. When
V
IN
rises above 17.5V, the regulator suspends operation
by shutting off both power MOSFETs on the correspond-
ing channel. Once V
IN
drops below 16.5V, the regulator
immediately resumes normal operation. The regulator
executes its soft-start function when exiting an overvolt
-
age condition.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configura
-
tion section of the data sheet are consistent with those
parameters defined by JESD51-9 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware test
board—also defined by JESD51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients in
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulators thermal performance in their ap
-
plication at various electrical and environmental operating
conditions to compliment any FEA activities
.
Without FEA
software, the thermal resistances reported in the Pin Con
-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the

LTM4632EV#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Ultrathin, Triple Module Regulator for QDR-DDR SRAM
Lifecycle:
New from this manufacturer.
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